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publication number s71ws512ne0bfwzz_00 revision a amendment 1 issue date june 28, 2004 advance information distinctive characteristics mcp features ? operating voltage range of 1.65 to 1.95 v ? high performance ? speed: 54mhz ? packages ? 96-ball fbga?9 x 12 mm ? operating temperatures ? wireless: ?25c to +85c general description the s71ws512 series is a product line of stacked multi-chip products (mcp) and consists of ? one or more s29ws256n (simultaneous operation, burst mode) flash die ? psram options ? 128mb psram the products covered by this document are listed below. for details about their specifications, please refer to the individual constituent data sheets for further details. mcp number of s29wsxxxn total flash density psram density s71ws512ne0 2 512mb 256mb notes: 1. this mcp is only guaranteed to operate @ 1.65 - 1.95 v regardless of component operating ranges. s71ws512ne0bfwzz stacked multi-chip product (mcp) flash memory and psram cmos 1.8 volt, simultaneous operation, burst mode flash memory and pseudo-static ram
2 s71ws512ne0bfwzz s71ws512ne0bfwzz_00_a1 june 28, 2004 advance information product selector guide device-model # sram/psram density sram/psram type supplier flash access time (mhz) ram access time (mhz) packages s71ws512ne0bfwzz 256mb psram - x16 cosmoram 1 54 54 tbd
june 28, 2004 s71ws512ne0bfwzz_00_a1 3 advance information table of contents s71ws512ne0bfwzz distinctive characteristics . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 product selector guide . . . . . . . . . . . . . . . . . . . . . .2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 mcp block diagram of s71ws512ne0bfwzz ...........................................6 connection diagrams . . . . . . . . . . . . . . . . . . . . . . 7 connection diagram of s71ws512ne0bfwzz ..........................................7 special package handling instructions ........................................................8 pin description ..................................................................................................8 logic symbol .....................................................................................................9 device bus operation ....................................................................................... 10 table 1. device bus operations ........................................... 10 pin capacitance ................................................................................................... 12 physical dimensions tbd . . . . . . . . . . . . . . . . . . 13 xxx .........................................................................................................................13 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) distinctive characteristics . . . . . . . . . . . . . . . . . . 14 general description . . . . . . . . . . . . . . . . . . . . . . . . 16 product selector guide . . . . . . . . . . . . . . . . . . . . 19 block diagram .................................................................................................... 19 block diagram of simultaneous operation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 input/output descriptions . . . . . . . . . . . . . . . . . . . 21 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 device bus operations . . . . . . . . . . . . . . . . . . . . . . 23 table 2. device bus operations ........................................... 23 requirements for asynchronous read operation (non-burst) ..........23 requirements for synchronous (burst) read operation ...................... 24 table 3. address dependent additional latency ..................... 24 continuous burst ........................................................................................... 24 8-, 16-, and 32-word linear burst with wrap around ......................25 table 4. burst address groups ............................................ 25 8-, 16-, and 32-word linear burst without wrap around ................25 configuration register ......................................................................................25 handshaking ..........................................................................................................25 simultaneous read/write operations with zero latency ................... 26 writing commands/command sequences ................................................ 26 unlock bypass mode .................................................................................... 26 accelerated program/erase operations ..................................................... 26 write buffer programming operation .........................................................27 autoselect mode ................................................................................................ 28 advanced sector protection and unprotection ....................................... 29 persistent mode lock bit ............................................................................ 29 password mode lock bit ............................................................................. 30 sector protection ............................................................................................... 30 persistent sector protection .......................................................................... 30 persistent protection bit (ppb) ...................................................................31 persistent protection bit lock (ppb lock bit) in persistent sector protection mode ..............................................................................................31 dynamic protection bit (dyb) ....................................................................31 table 5. sector protection schemes ..................................... 32 password sector protection ............................................................................ 33 64-bit password ...............................................................................................33 persistent protection bit lock (ppb lock bit) in password sector protection mode .............................................................................................33 lock register ....................................................................................................... 34 table 6. lock register ........................................................ 34 hardware data protection mode ................................................................. 34 write protect (wp#) ................................................................................... 34 low v cc write inhibit ................................................................................. 34 write pulse ?glitch? protection ............................................................... 35 logical inhibit ................................................................................................... 35 power-up write inhibit ............................................................................... 35 standby mode ...................................................................................................... 35 automatic sleep mode ..................................................................................... 35 reset#: hardware reset input ................................................................ 35 output disable mode ................................................................................... 36 secsi? (secured silicon) sector flash memory region .......................... 36 factory locked: factor secsi sector programmed and protected at the factory ....................................................................................................... 36 table 7. secsi tm sector addresses ........................................ 37 customer secsi sector ................................................................................. 37 secsi sector protection bit ......................................................................... 37 common flash memory interface (cfi) . . . . . . 37 table 8. cfi query identification string ................................ 38 table 9. system interface string ......................................... 38 table 10. device geometry definition ................................... 39 table 11. primary vendor-specific extended query ................ 39 table 12. sector address / memory address map for the ws256n ........................................................................................ 41 command definitions . . . . . . . . . . . . . . . . . . . . . . 49 reading array data ........................................................................................... 49 set configuration register command sequence .....................................49 read configuration register command sequence ..................................50 figure 1. synchronous/asynchronous state diagram.............. 50 read mode setting .........................................................................................50 programmable wait state configuration ............................................... 50 table 13. programmable wait state settings ......................... 51 programmable wait state ............................................................................ 51 boundary crossing latency ......................................................................... 51 set internal clock frequency ...................................................................... 51 table 14. wait states for handshaking ................................. 51 handshaking ...................................................................................................... 51 burst sequence ............................................................................................... 52 burst length configuration ......................................................................... 52 table 15. burst length configuration ................................... 52 burst wrap around ...................................................................................... 52 burst active clock edge configuration .................................................. 52 rdy configuration ........................................................................................ 52 rdy polarity .................................................................................................... 52 configuration register ...................................................................................... 53 table 16. configuration register .......................................... 53 reset command ................................................................................................. 53 autoselect command sequence .................................................................... 54 table 17. autoselect addresses ........................................... 54 enter secsi? sector/exit secsi sector command sequence ................ 55 word program command sequence ........................................................... 55 write buffer programming command sequence ..................................... 56 table 18. write buffer command sequence .......................... 56 figure 2. write buffer programming operation ...................... 57 unlock bypass command sequence ........................................................ 57 figure 3. program operation ............................................... 58
4 s71ws512ne0bfwzz_00_a1 june 28, 2004 advance information chip erase command sequence ................................................................... 58 sector erase command sequence .................................................................59 erase suspend/erase resume commands .................................................. 60 figure 4. erase operation.................................................... 61 program suspend/program resume commands ...................................... 61 lock register command set definitions ................................................... 62 password protection command set definitions ..................................... 62 non-volatile sector protection command set definitions ..................63 global volatile sector protection freeze command set ..................... 64 volatile sector protection command set ...................................................65 secsi sector entry command .........................................................................65 command definition summary ..................................................................... 66 write operation status . . . . . . . . . . . . . . . . . . . . .69 dq7: data# polling ........................................................................................... 69 figure 5. data# polling algorithm......................................... 70 rdy: ready .......................................................................................................... 70 dq6: toggle bit i ............................................................................................... 70 figure 6. toggle bit algorithm.............................................. 71 dq2: toggle bit ii ...............................................................................................72 table 19. dq6 and dq2 indications ..................................... 72 reading toggle bits dq6/dq2 ......................................................................72 dq5: exceeded timing limits ........................................................................73 dq3: sector erase timer .................................................................................73 dq1: write to buffer abort ............................................................................73 table 20. write operation status ......................................... 74 absolute maximum ratings . . . . . . . . . . . . . . . . . . 75 figure 7. maximum negative overshoot waveform ................. 75 figure 8. maximum positive overshoot waveform .................. 75 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 75 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . .76 cmos compatible .............................................................................................76 test conditions ...................................................................................................77 figure 9. test setup ........................................................... 77 table 21. test specifications ............................................... 77 switching waveforms ........................................................................................77 table 22. key to switching waveforms ................................. 77 figure 10. input waveforms and measurement levels............. 77 v cc power-up ..................................................................................................... 78 figure 11. v cc power-up diagram ........................................ 78 pin capacitance .................................................................................................. 78 ac characteristics?synchronous . . . . . . . . . . . 79 clk characterization ........................................................................................79 figure 12. clk characterization ........................................... 79 synchronous/burst read @ v io = 1.8 v ..................................................... 80 timing diagrams .................................................................................................. 81 figure 13. clk synchronous burst mode read (rising active clk). ....................................................................................... 81 figure 14. synchronous burst mode read.............................. 82 figure 15. eight-word linear burst with wrap around ............. 82 figure 16. eight-word linear burst without wrap around......... 83 figure 17. linear burst with rdy set one cycle before data .... 83 ac characteristics?asynchronous . . . . . . . . . . 84 asynchronous mode read @ v io ps = 1.8 v ............................................. 84 timing diagrams ................................................................................................. 84 figure 18. asynchronous mode read with latched addresses ... 84 figure 19. asynchronous mode read..................................... 85 hardware reset (reset#) .............................................................................. 85 figure 20. reset timings..................................................... 85 erase/program operations @ v io = 1.8 v ................................................. 86 figure 21. asynchronous program operation timings: we# latched addresses ............................................................. 87 figure 22. synchronous program operation timings: clk latched addresses......................................................................... 88 figure 23. accelerated unlock bypass programming timing..... 88 figure 24. data# polling timings (during embedded algorithm) ... ........................................................................................ 89 figure 25. toggle bit timings (during embedded algorithm) ... 89 figure 26. synchronous data polling timings/toggle bit timings .. ........................................................................................ 90 figure 27. dq2 vs. dq6 ..................................................... 90 figure 28. latency with boundary crossing when frequency > 66 mhz ................................................................................. 91 figure 29. latency with boundary crossing into program/erase bank................................................................................ 91 figure 30. example of wait states insertion.......................... 92 figure 31. back-to-back read/write cycle timings ................ 92 erase and programming performance . . . . . . . . 93 128mb psram features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 function truth table . . . . . . . . . . . . . . . 95 asynchronous operation (page mode) ..................................................... 95 function truth table (continued) . . . . 96 synchronous operation (burst mode) .......................................................96 state diagram . . . . . . . . . . . . . . . . . . . . . . . . .97 functional description . . . . . . . . . . . . . 98 power-up ...............................................................................................................98 configuration register ......................................................................................98 cr set sequence ................................................................................................98 functional description (continued) . . 99 address key ......................................................................................................... 99 functional description (continued) . 100 power down ...................................................................................................... 100 functional description (continued) . . 101 burst read/write operation ..........................................................................101 functional description (continued) . 102 clk input function ..........................................................................................102 adv# input function .......................................................................................102 wait# output function ................................................................................102 functional description (continued) . . 103 latency ..................................................................................................................103 functional description (continued) . 104 address latch by adv# .................................................................................104 burst length ........................................................................................................104 single write .........................................................................................................104 write control ....................................................................................................105 functional description (continued) . 106 burst read suspend ..........................................................................................106 burst write suspend ........................................................................................106 functional description (continued) . . 107 burst read termination ..................................................................................107 burst write termination ................................................................................107 absolute maximum ratings (see warning below.) . . . . . . . . . . . . . . . . . . . . . . 108 recommended operating conditions (see warning below.) . . . . . . . . . . . . . . . . . . 108 (referenced to vss) ................................................................................... 108 dc characteristics . . . . . (under recommended operating conditions unless otherwise noted) . . . . . . . . note *1,*2,*3 109
june 28, 2004 s71ws512ne0bfwzz_00_a1 5 advance information ac characteristics (under recommended operating conditions unless otherwise noted) . . . . . . . . . . . . . . . . . . . . 110 asynchronous read operation (page mode) ................110 ac characteristics (continued) . . . . . . . . 111 asynchronous write operation ............................................. 111 ac characteristics (continued) . . . . . . . . 112 synchronous operation - clock input (burst mode) ............................................................................................................................... ... 112 synchronous operation - address latch (burst mode) ............................................................................................................................... ... 112 ac characteristics (continued) . . . . . . . . 113 synchronous read operation (burst mode) ................ 113 ac characteristics (continued) . . . . . . . . 114 synchronous write operation (burst mode) .............. 114 ac characteristics (continued) . . . . . . . . 115 power down parameters ............................................................... 115 other timing parameters ................................................................. 115 ac characteristics (continued) . . . . . . . . 116 ac test conditions ............................................................................... 116 ac measurement output load circuit ................................. 116 timing diagrams . . . . . . . . . . . . . . . . . . . . . . 117 asynchronous read timing #1-1 (basic timing) ...................................... 117 asynchronous read timing #1-2 (basic timing) ...................................... 117 timing diagrams (continued) . . . . . . . . . . . 118 asynchronous read timing #2 (oe# & address access) ................... 118 asynchronous read timing #3 (lb# / ub# byte access) ..................118 timing diagrams (continued) . . . . . . . . . . . 119 asynchronous read timing #4 (page address access after ce#1 control access) .................................................................................................................. 119 asynchronous read timing #5 (random and page address access) 119 timing diagrams (continued) . . . . . . . . . . 120 asynchronous write timing #1-1 (basic timing) ...................................120 asynchronous write timing #1-2 (basic timing) ...................................120 timing diagrams (continued) . . . . . . . . . . . 121 asynchronous write timing #2 (we# control) ................................... 121 asynchronous write timing #3-1 (we# / lb# / ub# byte write con - trol) ........................................................................................................................ 1 21 timing diagrams (continued) . . . . . . . . . . 122 asynchronous write timing #3-2 (we# / lb# / ub# byte write con - trol) ....................................................................................................................... 12 2 asynchronous write timing #3-3 (we# / lb# / ub# byte write con - trol) ....................................................................................................................... 12 2 timing diagrams (continued) . . . . . . . . . . 123 asynchronous write timing #3-4 (we# / lb# / ub# byte write con - trol) ....................................................................................................................... 12 3 timing diagrams (continued) . . . . . . . . . . . 124 asynchronous read / write timing #1-1 (ce#1 control) ...................124 asynchronous read / write timing #1-2 (ce#1 / we# / oe# control) ............................................................................................................................... ... 124 timing diagrams (continued) . . . . . . . . . . . 125 asynchronous read / write timing #2 (oe#, we# control) ........125 asynchronous read / write timing #3 (oe#, we#, lb#, ub# control) ............................................................................................................................... ... 125 timing diagrams (continued) . . . . . . . . . . . 126 clock input timing ..........................................................................................126 address latch timing (synchronous mode) ............................................126 timing diagrams (continued) . . . . . . . . . . . 127 synchronous read timing #1 (oe# control) .........................................127 timing diagrams (continued) . . . . . . . . . . . 128 synchronous read timing #2 (ce#1 control) ........................................128 timing diagrams (continued) . . . . . . . . . . . 129 synchronous read timing #3 (adv# control) .....................................129 timing diagrams (continued) . . . . . . . . . . . 130 synchronous write timing #1 (we# level control) ...........................130 timing diagrams (continued) . . . . . . . . . . . 131 synchronous write timing #2 (we# single clock pulse control) .. 131 timing diagrams (continued) . . . . . . . . . . . 132 synchronous write timing #3 (adv# control) ................................... 132 timing diagrams (continued) . . . . . . . . . . . 133 synchronous write timing #4 (we# level control, single write) 133 timing diagrams (continued) . . . . . . . . . . . 134 synchronous read to write timing #1(ce#1 control) .......................134 timing diagrams (continued) . . . . . . . . . . . 135 synchronous read to write timing #2(adv# control) .................... 135 timing diagrams (continued) . . . . . . . . . . . 136 synchronous write to read timing #1 (ce#1 control) ......................136 timing diagrams (continued) . . . . . . . . . . . 137 synchronous write to read timing #2 (adv# control) .................. 137 timing diagrams (continued) . . . . . . . . . . . 138 power-up timing #1 ....................................................................................138 power-up timing #2 ...................................................................................138 timing diagrams (continued) . . . . . . . . . . . 139 power down entry and exit timing ..................................................139 standby entry timing after read or write ..............................................139 timing diagrams (continued) . . . . . . . . . . . 140 configuration register set timing #1 (asynchronous operation) ...140 timing diagrams (continued) . . . . . . . . . . . 141 configuration register set timing #2 (synchronous operation) .....141 revision summary
6 s71ws512ne0bfwzz_00_a1 june 28, 2004 advance information block diagrams mcp block diagram of s71ws512ne0bfwzz reset# v ss v ccps 256 m bit burst 128 m bit psram_1 ce#f2 a 23 to a 0 v ss v cc f_2 a 22 to a 0 dq 15 to dq 0 lb# ub# wp# 256 m bit burst v ss v cc f_1 a 23 to a 0 ce#f1 rdy flash memory_1 flash memory_2 128 m bit psram_2 we# avd# clk acc vio ps v ss v ccps vio ps oe# ce#1ps-2 ce2ps-2 ce#1ps-1 ce2ps-1
june 28, 2004 s71ws512ne0bfwzz_00_a1 7 advance information connection diagrams connection diagram of s71ws512ne0bfwzz e2 f2 g2 h2 j2 d3 e3 f3 g3 h3 j3 k3 d4 e4 f4 g4 h4 j4 k4 d5 e5 f5 j5 k5 l5 d6 e6 f6 j6 k6 l6 d7 e7 f7 g7 h7 j7 k7 d8 e8 f8 g8 h8 j8 k8 e9 f9 g9 h9 j9 rfu l7 dq5 l8 dq14 dq11 m5 m6 rfu vcc f_2 a3 a2 a1 a0 ce#f1 a7 a6 a5 a4 vss oe# dq0 lb# ub#s a18 a17 dq1 dq9 dq10 k2 l3 l4 ce#1ps_1 dq8 dq2 acc rst#f rdy dq3 vccf_1 we# c5 c6 ce#f2 rfu ce2p s_ 1 a20 g5 g6 ce#1p s 2 a23 h5 h6 vccp s ce2ps_2 dq4 viop s a8 a19 a9 a10 dq6 dq13 dq12 a11 c3 c4 c7 c8 vss clk rfu rfu a12 a13 a14 rfu dq15 dq7 k9 vss l2 rfu l9 rfu m7 rfu m8 rfu m3 m4 rfu vss m2 rfu m9 rfu n2 nc n9 nc n1 nc n10 nc p2 nc p9 nc p1 nc p10 nc a15 d2 d9 wp# rfu c2 c9 avd# rfu b2 b9 nc nc b1 b10 nc nc a2 a9 nc nc a1 a10 nc nc a21 a22 a16 rfu 96-ball fbga to p v i e w
8 s71ws512ne0bfwzz_00_a1 june 28, 2004 advance information special package handling instructions special handling is required for flash memory products in molded packages (fbga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. pin description a22?a0 = 23 address inputs (common) a23 = 1 address inputs (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f = chip enable (flash) ce#1ps = chip enable1 (psram) ce#2ps = chip enable2 (psram) oe# = output enable (common) we# = write enable (common) rdy = ready output clk = clock input avd# = address valid input ub# = upper byte control (sram) lb# = lower byte control (sram) reset# = hardware reset pin, active low (flash) wp# = hardware write protect (flash) acc = acceleration pin (flash) v cc f = flash 1.8 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ccp s = psram power supply vio p s = psram output buffer power supply v ss = device ground (common) nc = pin not connected internally rfu = reserved for future use
june 28, 2004 s71ws512ne0bfwzz_00_a1 9 advance information logic symbol ? nor flash and psram and data storage densities up to 4 gigabits the signal locations of the resultant mcp device are shown ab ove. note that for different densities, the actual package outline may vary. any pinout in any mcp, however, will be a subset of the pinout above. in some cases, there may be outrigger balls in locations outside the grid shown above. in such cases, the user is rec- ommended to treat them as reserved and not connect them to any other signal. for any further inquiries about the above look-ahead pinout, please refer to the ap - plication note on this subject or contact your sales office. 23 16 dq15?dq0 a22?a0 ce#f oe# we# reset# ub# rdy wp#/acc a23 lb# ce1#ps ce2s
10 s71ws512ne0bfwzz_00_a1 june 28, 2004 advance information device bus operation legend: l = logic 0, h = logic 1, x = don?t care. note: default active edge of clk is the rising edge. ordering information ta b l e 1 . device bus operations operation (asynchronous) - flash ce#f1 ce#f2 ce#1ps_1 ce2ps_1 ce#1ps_2 ce2ps_2 oe# we# addr dq15- dq0 ub# lb# reset# wp# acc# clk(see note) avd# read - address latched l h h l h l l h valid valid x x h h h x h l h h h h read - address steady state l h h l h l l h valid valid x x h h h x l h l h h h h write l h h l h l h l valid valid x x h h h x l h l h h h h standby h h h h h h x x x high-z x x h h h x x reset x x x x x x x x x high-z x x l h h x x output disable h h l h h h h h x x x x h h h x x h l h h h h l h h h h h operation(synchronous) - flash ce#f1 ce#f2 ce#1ps_1 ce2ps_1 ce#1ps_2 ce2ps_2 oe# we# addr dq15- dq0 ub# lb# reset# wp# acc# clk(see note) avd# load starting burst adress l h h l h l x h valid data x x h h h h l h h h h advance burst read to next address l h h l h l l h x data x x h h h h h l h h h h terminate current burst read cycle h h h h h h x h x high-z x x h h h x "terminate current burst read cycle via reset#" x x x x x x x h x high-z x x l h h x x "terminate current burst read cycle and start new burst read cycle" l h h l h l x h valid valid x x h h h h l h h h h operation (asyncronous) - psram ce#f1 ce#f2 ce#1ps_1 ce2ps_1 ce#1ps_2 ce2ps_2 oe# we# addr dq15- dq0 ub# lb# reset# wp# acc# clk(see note) avd# read h h l h h h l h valid valid l l h h h x h/l h h h h l h read (page) h h l h h h l h valid valid h/l h/l h h h x h/l h h h h l h write h h l h h h h l valid valid l l h h h x *note h h h h l h write(upper byte) h h l h h h h l valid invalid( dq0-8) l h h h h x *note h h h h l h valid(dq 9-15) write(lower byte) h h l h h h h l valid valid(dq 0-8) h l h h h x *note h h h h l h invalid( dq9-15) standby h h h h h h h h x high-z x x h h h x *note powerdown h h x l x l x x x high-z x x h h h x x output disable h h l h l h h h x x x x h h h x *note operation(syncronous) - psram ce#f1 ce#f2 ce#1ps_1 ce2ps_1 ce#1ps_2 ce2ps_2 oe# we# addr dq15- dq0 ub# lb# reset# wp# acc# clk(see note) avd# load starting burst adress h h h l h h x h valid data x x h h h h h h h h l advance burst read to next address h h h l h h l h x data x x h h h h h h h h h l terminate current burst read cycle h h h h h h x h x high-z x x h h h x "terminate current burst read cycle and start new burst read cycle" h h h l h l x h valid valid x x h h h h h h h h h
june 28, 2004 s71ws512ne0bfwzz_00_a1 11 advance information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local sales office to confirm availa bility of specific valid combinations and to check on newly released combinations. s71ws512ne0bfwzz0 packing type 0=tray 2=7? tape & reel 3 = 13? tape & reel additional ordering options see product selector guide temperature (and reliability) grade e = engineering samples w = wireless (-25 c to +85 c) i = industrial (-40 c to +85 c) package material set (bga package type) a = standard (pb-free compliant) package f = lead (pb)-free package package type b=bga package chip contents?2 0 = no second content chip contents?1 8=8 mb a = 16 mb b = 32 mb c = 64 mb e = 256 mb (two 128mb) spansion flash memory process technology (highest-density flash described in characters 4-8) n = 110 nm mirrorbit tm technology base nor flash density 512 = two s29ws256n base nor flash core voltage s = 1.8-volt v cc base nor flash interface and simultaneous read/ write w = simultaneous read/write, burst product family 71 = flash base + xram. prefix s=spansion
12 s71ws512ne0bfwzz_00_a1 june 28, 2004 advance information pin capacitance valid combinations flash access time (mhz) (p)sram access time (mhz) te m p e r a t u r e range supplier order number package marking s71ws512ne0bfwzz 71ws512ne0bfwzz 54 54 -25c to +85c supplier 1 symbol parameter test condition ty p max unit c in1 input capacitance v in =0 tbd tbd pf c in2 output capacitance v out =0 tbd tbd pf c out control capacitance v in =0 tbd tbd pf
june 28, 2004 s71ws512ne0bfwzz_00_a1 13 advance information physical dimensions tbd xxx
14 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s29ws256n 256 megabit (16 m x 16-bit) cmos 1.8 volt-only simultaneous read/write, burst mode flash memory distinctive characteristics architectural advantages ? single 1.8 volt read, program and erase (1.65 to 1.95 volt) ? manufactured on 110 nm mirrorbit tm process technology ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency between read and write operations ? sixteen bank architecture: each bank consists of 16mb (ws256n) ? programable burst interface ? 2 modes of burst read operation ? linear burst: 32, 16, and 8 words with or without wrap-around ? continuous sequential burst ? secsi tm (secured silicon) sector region ? 256 words accessible through a command sequence, 128 words for the factory secsi sector and 128 words for the customer secsi sector. ? sector architecture ? s29ws256n: eight 16 kword sectors and two- hundred-fifty-four 64 kword sectors ? banks 0 and 15 each contain 16 kword sectors and 64 kword sectors; other banks each contain 64 kword sectors ? eight 16 kword boot sectors, four at the top of the address range, and four at the bottom of the address range ? 100,000 erase cycles per sector typical ? 20-year data retention typical performance characteristics ? read access times at 66/54 mhz @ 1.8v v io (1.65 - 1.95v) ? burst access times of 11.2/13.5 ns for 1.8v v io (@ 30 pf at industrial temperature range) ? synchronous initial latency of 69/69 ns for 1.8v v io (@ 30 pf at industrial temperature range) ? asynchronous random access times of 70/70 ns for 1.8v v io (@ 30 pf at industrial temperature range) ? high performance ? typical word programming time of < 40 s ? typical effective word programming time of <9.4 s utilizing a 32-word write buffer at vcc level ? typical effective word programming time of <4 s utilizing a 32-word write buffer at acc level ? typical sector erase time of <150 ms for both 16 kword sectors and <400 ms sector erase time for 64 kword sectors ? power dissipation (typical values, c l = 30 pf) @ 66 mhz ? continuous burst mode read: <28 ma ? simultaneous operation: <50 ma ?program: <35 ma ?erase: <35 ma ? standby mode: <20 a hardware features ? sector protection ? write protect (wp#) function allows protection of eight outermost boot sectors, four at top and four at bottom of memory, regardless of sector protect status ? handshaking feature available ? provides host system with minimum possible latency by monitoring rdy ? hardware reset input (reset#) ? hardware method to reset the device for reading array data ? boot option ? dual boot ? cmos compatible inputs, cmos compatible outputs ? low v cc write inhibit security features ? advanced sector protection consists of the two following modes of operation ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level ? password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors to prevent program or erase operations within that sector using a user-defined 64-bit password software features ? supports common flash memory interface (cfi) ? software command set compatible with jedec 42.4 standards ? data# polling and toggle bits ? provides a software method of detecting program and erase operation completion
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 15 advance information ? erase suspend/resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? program suspend/resume ? suspends a programming operation to read data from a sector other than the one being programmed, then resume the programming operation ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences additional features ? program operation ? ability to perform synchronous and asynchronous program operation independent of burst control register setting ? acc input pin ? acceleration function reduces programming time in a factory setting.
16 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information general description the wsxxxn is a 256 mbit, 1.8 volt-only, simultaneous read/write, burst mode flash memory device, organized as 16 mwords of 16 bits. this device uses a sin - gle v cc of 1.65 to 1.95 v to read, program, and erase the memory array. a 9.0- volt v hh on acc may be used for faster program performance if desired. the de - vice can be programmed in standard eprom programmers. at 66 mhz and 1.8v v io , the device provides a burst access of 11.2 ns at 30 pf with am initial latency of 69 ns at 30 pf. at 54 mhz and 1.8v v io , the device pro - vides a burst access of 13.5 ns at 30 pf with an initial latency of 69 ns at 30 pf. the device operates within the industrial temperature range of -40c to +85c or wireless temperature range of -25c to +80c. these devices are offered in mcp compatible fbga packages. see the product selector guide for details the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into sixteen banks. the device can improve over - all system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. the device is divided as shown in the following table: the versatileio? (v io ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the v io pin. the device uses chip enable (ce#), write enable (we#), address valid (avd#) and output enable (oe#) to control asynchronous read and write operations. for burst operations, the device additionally requires ready (rdy), and clock (clk). this implementation allows easy interface with minimal glue logic to a bank quantity of sectors (ws256n) sector size 0 4/4/4 16 kwords 15/7/3 64 kwords 1 16/8/4 64 kwords 2 16/8/4 64 kwords 3 16/8/4 64 kwords 4 16/8/4 64 kwords 5 16/8/4 64 kwords 6 16/8/4 64 kwords 7 16/8/4 64 kwords 8 16/8/4 64 kwords 9 16/8/4 64 kwords 10 16/8/4 64 kwords 11 16/8/4 64 kwords 12 16/8/4 64 kwords 13 16/8/4 64 kwords 14 16/8/4 64 kwords 15 15/7/3 64 kwords 4/4/4 16 kwords
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 17 advance information wide range of microprocessors/microcontrollers for high performance read operations. the burst read mode feature gives system designers flexibility in the interface to the device. the user can preset the burst length and then wrap or non-wrap through the same memory space, or read the flash array in continuous mode. the clock polarity feature provides system designers a choice of active clock edges, either rising or falling. the active clock edge initiates burst accesses and determines when data will be output. the device is entirely command set compatible with the jedec 42.4 single- power-supply flash standard . commands are written to the command regis - ter using standard microprocessor write timing. register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the write buffer programming algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. this feature provides superior programming performance by grouping locations being programmed.the unlock bypass mode facilitates faster program times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase command sequence. this initiates the embedded erase algorithm - an internal algorithm that automatically pre - programs the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the program suspend/program resume feature enables the user to put program on hold for any period of time to read data from any sector that is not selected for programming. if a read is needed from the secsi sector area (one time program area), persistent protection area, dynamic protection area, or the cfi area, after an program suspend, then the user must use the proper com - mand sequence to enter and exit this region. the program suspend/resume functionality is also available when programming in erase suspend (1 level depth only). the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secsi sector area (one time program area), persis - tent protection area, dynamic protection area, or the cfi area, after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, en - abling the system microprocessor to read boot-up firmware from the flash memory device. the host system can detect whether a program or erase operation is complete by using the device status bit dq7 (data# polling), dq6/dq2 (toggle bits), dq5 (exceeded timing limit), dq3 (sector erase timer), and dq1 (write to buffer abort). after a program or erase cycle has been completed, the device automat - ically returns to reading array data.
18 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information the sector erase architecture allows memory sectors to be erased and repro - grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automat - ically inhibits write operations during power transitions. the device also offers two types of data protection at the sector level. when at v il , wp# locks the four outermost boot sectors at the top of memory and four outermost boot sec - tors at the bottom of memory. when the acc pin = v il , the entire flash memory array is protected. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consump - tion is greatly reduced in both modes. spansion tm flash memory products combine years of flash memory manufactur - ing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simulta - neously via fowler-nordheim tunnelling. the data is programmed using hot electron injection.
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 19 advance information product selector guide block diagram part number s29ws256n v io option 1.65?1.95 v speed option (burst frequency) (note 1) 66 mhz 54 mhz max synchronous latency, ns (t iacc ) 69 69 max synchronous burst access time, ns (t bacc ) 11.2 13.5 max asynchronous access time t ce ), ns 70 70 max ce# access time, ns (t ce ), ns 70 70 max oe# access time, ns (t oe ) 11.2 13.5 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v ssio v io we# reset# wp# acc ce# oe# dq15 ? dq0 data latch y-gating cell matrix address latch a max ?a0* rdy buffer rdy burst state control burst address counter avd# clk *ws256n: a23-a0
20 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information block diagram of simultan eous operation circuit notes: amax=a23 for the ws256n. v ss v cc v io bank address reset# acc we# ce# avd# rdy dq15?dq0 wp# state control & command register bank 1 x-decoder y-decoder latches and control logic bank 0 x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 bank 14 y-decoder x-decoder latches and control logic bank 15 y-decoder x-decoder latches and control logic oe# status control amax?a0 amax?a0 amax?a0 amax?a0 amax?a0 bank address bank address bank address
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 21 advance information input/output descriptions a23-a0 = address inputs for ws256n dq15-dq0 = data input/output ce# = chip enable input. asynchronous relative to clk for the burst mode. oe# = output enable input. asynchronous relative to clk for the burst mode. we# = write enable input. v cc = device power supply (1.65 ? 1.95 v). v io = input & output buffer power supply (1.35 ? 1.70 v). v ss = ground v ssio = output buffer ground nc = no connect; not connected internally rdy = ready output. indicates the status of the burst read. clk = clock input. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. should be at v il or v ih while in asynchronous mode avd# = address valid input. indicates to device that the valid address is present on the address inputs. low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. high = device ignores address inputs reset# = hardware reset input. low = device resets and returns to reading array data wp# = hardware write protect input. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. acc = accelerated input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions.
22 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information logic symbol max*+1 16 dq15?dq0 amax*?a0 ce# oe# we# reset# clk rdy avd# wp# acc * max=23 for the ws256n.
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 23 advance information device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is com - posed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. ta b l e 2 lists the device bus operations, the inputs and con - trol levels they require, and the resulting output. the following subsections describe each of these operations in further detail. legend: l = logic 0, h = logic 1, x = don?t care. note: default active edge of clk is the rising edge. requirements for asynchronous read operation (non- burst) to read data from the memory array, the system must first assert a valid address on a23?a0 for ws256n , while driving avd# and ce# to v il . we# should remain at v ih . the rising edge of avd# latches the address. the data will appear on dq15?dq0. since the memory array is divided into sixteen banks, each bank re - mains enabled for read access until the command register contents are altered. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad - dresses and stable ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output. the internal state machine is set for reading array data in asynchronous mode upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. ta b l e 2 . device bus operations operation ce# oe# we# addresses dq15?0 reset# clk (see note ) avd# asynchronous read - addresses latched l l h addr in i/o h x asynchronous read - addresses steady state l l h addr in i/o h x l asynchronous write l h l addr in i/o h x l synchronous write l h l addr in i/o h standby (ce#) h x x x high z h x x hardware reset x x x x high z l x x burst read operations (synchronous) load starting burst address l x h addr in x h advance burst to next address with appropriate data presented on the data bus l l h x burst data out h h terminate current burst read cycle h x h x high z h x terminate current burst read cycle via reset# x x h x high z l x x terminate current burst read cycle and start new burst read cycle l x h addr in i/o h
24 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information requirements for synchronous (burst) read operation the device is capable of continuous sequential burst read and linear burst read of a preset length. when the device first powers up, it is enabled for asynchro - nous read operation. prior to entering burst mode, the system should determine how many wait states are desired for the initial word (t iacc ) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the rdy signal will transition with valid data. the system would then write the configuration register command sequence. see " set configuration register command sequence " section for further details. once the system has written the ?set configuration register? command se - quence, the device is enabled for synchronous reads only. the initial word is output t iacc after the active edge of the first clk cycle. sub - sequent words are output t bacc after the active edge of each successive clock cycle at which point the internal address counter is automatically incremented. note that the device has a fixed internal address boundary that occurs every 128 words, starting at address 00007fh. no boundary crossing latency is required when the device operates at or below 66 mhz to reach address 000080h. when the device operates above 66 mhz, a boundary crossing of one additional wait state is required. the timing diagram can be found in figure 28 . when the starting burst address is not divisible by four, additional waits are re - quired. for example, if the starting burst address is divisible by four a1:0 = 00, no additional wait state is required, but if the starting burst address is at address a1:0 = 01, 10, or 11, one, two or three wait states are required, respectively, until data dq4 is read. the rdy output indicates this condition to the system by deasserting (see ta b l e 3 and ta b l e 1 3 ). continuous burst the device will continue to output sequential burst data, wrapping around to ad - dress 000000h after it reaches the highest addressable memory location, until the system drives ce# high, reset# low, or avd# low in conjunction with a new address. see ta b l e 2 . if the host system crosses a bank boundary while reading in burst mode, and the subsequent bank is not programming or erasing, a one-cycle latency is required as described above if the device is operating above 66 mhz. if the device is op - erating at or below 66 mhz, no boundary crossing latency is required. if the host system crosses the bank boundary while the subsequent bank is programming or erasing, the device will provide read status information. the clock will be ignored. after the host has completed status reads, or the device has completed the pro - gram or erase operation, the host can restart a burst operation using a new address and avd# pulse. ta b l e 3 . address dependent additional latency initial address a[10] cycle x x+1 x+2 x+3 x+4 x+5 x+6 00 dq0 dq1 dq2 d q 3 dq4 dq5 dq6 01 dq1 dq2 d q 3 -- dq4 dq5 dq6 10 dq2 d q 3 -- -- dq4 dq5 dq6 11 d q 3 -- -- -- dq4 dq5 dq6
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 25 advance information 8-, 16-, and 32-word linear burst with wrap around the remaining three burst read modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burst addresses read are determined by the group within which the starting address falls. the groups are sized according to the number of words read in a single burst sequence for a given mode (see ta b l e 4 .) for example, if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3fh, and the burst sequence would be 39-3a-3b-3c-3d- 3e-3f-38h if wrap around is enabled. the burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting addr ess written to the device, and then wrap back to the first address in the selected address group. note that in these three burst read modes the address pointer does not cross the boundary that occurs every 128 words; thus, no wait states are inserted (except during the initial access). (see figure 15 ) 8-, 16-, and 32-word linear burst without wrap around if wrap around is not enabled, 8-word, 16-word, or 32-word burst will execute linearly up to the maximum memory address of the selected number of words. the burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address of the selected group. for example: if the starting address in the 8- word mode is 39h, the address range to be read would be 39-40h, and the burst sequence would be 39-3a-3b-3c-3d-3e-3f-40 if wrap around is not enabled. the next address to be read will require a new address and avd# pulse. the rdy pin indicates when data is valid on the bus. configuration register the device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, rdy configuration, and synchronous mode active. for more information, see ta b l e 1 6 . handshaking the device is equipped with a handshaking feature that allows the host system to simply monitor the rdy signal from the device to determine when the burst data is ready to be read. the host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode oper - ation. the initial word of burst data is indicated by the rising edge of rdy after oe# goes low. for optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on clock frequency. see the " set configuration register command sequence " section and the " requirements for synchronous (burst) read operation " section for more information. ta b l e 4 . burst address groups mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h,... 16-word 16 words 0-fh, 10-1fh, 20-2fh,... 32-word 32 words 00-1fh, 20-3fh, 40-5fh,...
26 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information simultaneous read/write operations with zero latency this device is capable of reading data from one bank of memory while program - ming or erasing in another bank of memory. an erase operation may also be suspended to read from or program to another location within the same bank (except the sector being erased). figure 31 shows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc char - acteristics table for read-while-program and read-while-erase current specifications. writing commands/command sequences the device has the capability of performing an asynchronous or synchronous write operation. while the device is configured in asynchronous read it is able to perform asynchronous write operations only. clk is ignored when the device is configured in the asynchronous mode. when in the synchronous read mode con - figuration, the device is able to perform both asynchronous and synchronous write operations. clk and avd# induced address latches are supported in the synchronous programming mode. during a synchronous write operation, to write a command or command sequence (which includes programming data to the de - vice and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or data. during an asyn - chronous write operation, the system must drive ce# and we# to v il and oe# to v ih when providing an address, command, and data. addresses are latched on the last falling edge of we# or ce#, while data is latched on the 1st rising edge of we# or ce# (see ta b l e 1 6 ). an erase operation can erase one sector, multiple sectors, or the entire device. ta b l e 1 2 indicates the address space that each sector occupies. the device ad - dress space is divided into sixteen banks: banks 1 through 14 contain only 64 kword sectors, while banks 0 and 15 contain both 16 kword boot sectors in ad - dition to 64 kword sectors. a ?bank address? is the set of address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits re - quired to uniquely select a sector. i cc2 in ?dc characteristics? represents the active current specification for the write mode. ?ac characteristics?synchronous? and ?ac characteristics?asyn - chronous? contain timing specification tables and timing diagrams for write operations. unlock bypass mode the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are re - quired to program a set of words, instead of four. see the " unlock bypass command sequence " section for more details. accelerated program/erase operations the device offers accelerated program and accelerated chiperase operations through the acc function. acc is intended to allow faster manufacturing throughput at the factory and not to be used in system operations. if the system asserts v hh on this input, the device automatically enters the aforementioned unlock bypass mode and uses the higher voltage on the input to reduce the time required for program and erase operations. the system can then use the write buffer load command sequence provided by the unlock bypass mode. note that if a ?write-to-buffer-abort reset? is required while in unlock by -
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 27 advance information pass mode, the full 3-cycle reset command sequence must be used to reset the device . removing v hh from the acc input, upon completion of the embedded program or erase operation, returns the device to normal operation. note that sectors must be unlocked prior to raising acc to v hh . note that the acc pin must not be at v hh for operations other than accelerated programming and accelerated chip erase, or device damage may result. in addition, the acc pin must not be left floating or unconnected; inconsistent behavior of the device may result . when at v il , acc locks all sectors. acc should be at v ih for all other conditions. write buffer programming operation write buffer programming allows the system to write a maximum of 32 words in one programming operation. this results in a faster effective word program - ming time than the standard ?word? programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming will occur. at this point, the system writes the number of ? word locations minus 1 ? that will be loaded into the page buffer at the sector address in which programming will occur. this tells the device how many write buffer addresses will be loaded with data and there - fore when to expect the ?program buffer to flash? confirm command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. (note: the size of the write buffer is dependent upon which data are being loaded. also note that the number loaded = the number of locations to pro - gram minus 1. for example, if the system will program 6 address locations, then 05h should be written to the device.) the system then writes the starting address/data combination. this starting ad - dress is the first address/data pair to be programmed, and selects the ?write- buffer-page? address. all subsequent address/data pairs must fall within the ?se - lected-write-buffer-page?. the ?write-buffer-page? is selected by using the addresses a max - a5 where a max is a23 for ws256n. the ?write-buffer-page? addresses must be the same for all address/data pairs loaded into the write buffer . (this means write buffer programming cannot be performed across multiple ?write-buffer-pages?. this also means that write buffer programming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected ?write-buffer- page?, the operation will abort.) after writing the starting address/data pair, the system then writes the remain - ing address/data pairs into the write buffer. write buffer locations may be loaded in any order. note that if a write buffer address location is loaded multiple times, the ?address/ data pair? counter will be decremented for every data load operation . also, the last data loaded at a location before the ?program buffer to flash? confirm command will be programmed into the device. it is the software?s responsibility to comprehend ramifications of loading a write-buffer location more than once. the counter decrements for each data load operation , not for each unique write-buffer-address location . once the specified number of write buffer locations have been loaded, the system must then write the ?program buffer to flash? command at the sector address.
28 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information any other address/data write combinations will abort the write buffer program - ming operation. the device will then ?go busy.? the data bar polling techniques should be used while monitoring the last address locati on loaded into the write buffer . this eliminates the need to store an address in memory because the system can load the last address location, issue the program confirm com - mand at the last loaded address location, and then data bar poll at that same address. dq7, dq6, dq5, dq2, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer ?embedded? programming operation can be suspended using the standard suspend/resume commands. upon successful completion of the write buffer programming operation, the device will return to read mode. the write buffer programming sequence is aborted under any of the following conditions: ? load a value that is greater than the page buffer size during the ?number of locations to program? step. ? write to an address in a sector different than the one specified during the ?write-buffer-load? command. ? write an address/data pair to a different write-buffer-page than the one se - lected by the ?starting address? during the ?write buffer data loading? stage of the operation. ? write data other than the ?confirm command? after the specified number of ?data load? cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the ?last ad - dress location loaded?), dq6 = toggle, dq5 = 0. this indicates that the write buffer programming operation was aborted. a ?write-to-buffer-abort reset? command sequence is required when using the write-buffer-programming fea - tures in unlock bypass mode. note that the secsi tm sector, autoselect, and cfi functions are unavailable when a program operation is in progress. write buffer programming is allowed in any sequence of memory (or address) lo - cations. these flash devices are capable of handling multiple write buffer programming operations on the same write buffer address range without inter - vening erases. however, programming the same word address multiple times without intervening erases requires a modified programming method. please con - tact your local spansion tm representative for details. use of the write buffer is strongly recommended for programming when multiple words are to be programmed. write buffer programming is approximately eight times faster than programming one word at a time. autoselect mode the autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output from the internal register (separate from the memory array) on dq15?dq0. this mode is primarily in - tended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. the autoselect codes can also be accessed in-system. when verifying sector protection, the sector address must appear on the appro - priate highest order address bits (see ta b l e 1 2 ). the remaining address bits are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on dq15?dq0. the autoselect codes can also be accessed in-system through the command register. the command sequence is illustrated in the " command definition summary " sec -
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 29 advance information tion . note that if a bank address (ba) on the four uppermost address bits is asserted during the third write cycle of the autoselect command, the host system can read autoselect data from that bank and then immediately read array data from the other bank, without exiting the autoselect mode. to access the autoselect codes, the host system must issue the autoselect com - mand via the command register, as shown in the " command definition summary " section . refer to the " autoselect command sequence " section for more information. advanced sector protection and unprotection this advanced security feature provides an additional level of protection to all sectors against inadvertant program or erase operations. the advanced sector protection feature disables both programming and erase op - erations in a sector while the advanced sector unprotection feature re-enables both program and erase operations in previously protected sectors. sector pro - tection/unprotection can be implemented using either or both of the two methods ? hardware method ? software method persistent/password sector protection is achieved by using the software method while the sector protection with wp# pin is achieved by using the hardware method. all parts default to operate in the persistent sector protection mode. the cus - tomer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method will be used. ? persistent mode lock bit ? password mode lock bit if the customer decides to continue using the persistent sector protection method, they must set the persistent mode lock bit . this will permanently set the part to operate using only persistent sector protection. however, if the cus - tomer decides to use the password sector protection method, they must set the password mode lock bit . this will permanently set the part to operate using only password sector protection. it is important to remember that setting either the persistent mode lock bit or the password mode lock bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit has been set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. if both are selected to be set at the same time, the operation will abort. this is done so that it is not possible for a system program or virus to later set the pass - word mode locking bit, which would cause an unexpected shift from the default persistent sector protection mode into the password sector protection mode. the device is shipped with all sectors unprotected. optional spansion tm program - ming services enable programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for more details. persistent mode lock bit a persistent mode lock bit exists to guarantee that the device remain in software sector protection. once programmed (set to ?0?), the persistent mode lock bit prevents programming of the password mode lock bit. this allows protection
30 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information from potential hackers locking the device by placing the device in password sec - tor protection mode and then changing the password accordingly. password mode lock bit in order to select the password sector protection scheme, the customer must first program the password. spansion llc recommends that the password be some - how correlated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each pass - word should be different for every flash device. while programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: 1.it permanently sets the device to operate using the password sector protection mode. it is not possible to reverse this function. 2.it also disables all further commands to the password region. all program and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password sector protec - tion method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the pass - word mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is after it is set. if the password is lost after setting the password mode lock bit, there will be no way to clear the ppb lock bit. the password mode lock bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode lock bit is not erasable. once the password mode lock bit is programmed, the persistent mode lock bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. sector protection the device features several levels of sector protection, which can disable both the program and erase operations in certain sectors. ? persistent sector protection: a software enabled command sector protection method that replaces the old 12 v controlled protection method. ? password sector protection: a highly sophisticated software enabled protec - tion method that requires a password before changes to certain sectors or sector groups are permitted ? wp# hardware protection: a write protect pin (wp#) can prevent program or erase operations in the outermost sectors.the wp# hardware protection fea - ture is always available, independent of the software managed protection method chosen. persistent sector protection the persistent sector protection method replaces the old 12 v controlled protec - tion method while at the same time enhancing flexibility by providing three different sector protection states: ? persistently locked?a sector is protected and cannot be changed. ? dynamically locked?the sector is protected and can be changed by a simple command
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 31 advance information ? unlocked?the sector is unprotected and can be changed by a simple com - mand in order to achieve these states, three types of ?bits? namely persistent protec - tion bit (ppb), dynamic protecton bit (dyb), and persistent protection bit lock (ppb lock) are used to achieve the desired sector protection scheme persistent protection bit (ppb) ppb is used to as an advanced security feature to protect individual sectors from being programmed or erased thereby providing additional level of protection. every sector is assigned a persistent protection bit. each ppb is individually programmed through the ppb program command . however all ppbs are erased in parallel through the all ppb erase command . prior to erasing, these bits dont have to be preprogrammed. the embedded erase algorithm automatically preprograms and veri fies prior to an electrical erase. the system is not required to provide any controls or timings during these operations. the ppbs retain their state across power cycles because they are non-volatile. the ppbs have the same endurance as the flash memory. persistent protection bit lock (ppb lock bit) in persistent sector protection mode ppb lock bit is a global volatile bit and provides an additional level of protection to the sectors. when programmed (set to ?0?) , all the ppbs are locked and hence none of them can be changed. when erased (cleared to ?1?) , the ppbs are changeable. there is only one ppb lock bit in every device. only a hardware reset or a power-up clears the ppb lock bit. it is to be noted that there is no soft - ware solution, ie. command sequence to unlock the ppb lock bit. once all ppbs are set (programmed to ?0?) to the desired settings, the ppb lock bit may be set (programmed to ?0?). the ppb lock bit is set by issuing the ppb lock bit set command. programming or setting the ppb lock bit disables pro - gram and erase commands to all the ppbs. in effect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock bit is to go through a hardward or powerup reset. system boot code can determine if any changes to the ppb are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can disable the ppb lock bit to pre - vent any further changes to the ppbs during system operation. dynamic protection bit (dyb) dyb is another security feature used to protect individual sectors from being pro - grammed or erased inadvertantly. it is a volatile protection bit and is assigned to each sector. each dyb can be individually modified through the dyb set com - mand or the dyb clear command. the protection status for a particular sector is determined by the status of the ppb and the dyb relative to that sector. for the sectors that have the ppbs cleared (erased to ?1?), the dybs control whether or not the sector is protected or unpro - tected. by issuing the dyb set or clear command sequences, the dybs will be set (programmed to ?0?) or cleared (erased to ?1?), thus placing each sector in the protected or unprotected state respectively. these states are the so-called dy - namic locked or unlocked states due to the fact that they can switch back and forth between the protected and unprotected states. this feature allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dybs maybe set (pro - grammed to ?0?) or cleared (erased to ?1?) as often as needed.
32 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information when the parts are first shipped, the ppbs are cleared (erased to ?1?) and upon power up or reset, the dybs are set or cleared depending upon the ordering op - tion chosen. if the option to clear the dybs after power up is chosen, (erased to ?1?), then the sectors may be modified depending upon the ppb state of that sec - tor. (see ta b l e 5 ) if the option to set the dybs after power up is chosen (programmed to ?0?), then the sectors would be in the protected state. the ppb lock bit defaults to the cleared state (erased to ?1?) after power up and the ppbs retain their previous state as they are non-volatile. the default dyb state is cleared (erased to ?1?) with the sectors in the unprotected state. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb set command sequence is all that is necessary. the dyb set or clear command for the dynamic sectors signify protected or unprotected state of the sectors respectively. however, if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bi t must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the device operates normally again. note: to achieve the best protection, it?s recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp# = v il . note that the ppb and dyb bits have the same function when acc = vhh as they do when acc = v ih . ta b l e 5 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set (programmed to ?0?), and the ppb lock is set (pro - grammed to ?0?), the sector is protected and the protection can not be removed until the next power cycle clears (erase to ?1?) the ppb lock bit. once the ppb lock bit is cleared (erased to ?1?), the sector can be persistently locked or un - locked. likewise, if both ppb lock bit or ppb is cleared (erased to ?1?) the sector can then be dynamically locked or unlocked. the dyb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program or erase command to a pro - ta b l e 5 . sector protection schemes dy b ppb ppb lock sector state 1 1 1 sector unprotected 0 1 1 sector protected through dyb 1 0 1 sector protected through ppb 0 0 1 sector protected through ppb and dyb 1 1 0 sector unprotected 0 1 0 sector protected through dyb 1 0 0 sector protected through ppb 0 0 0 sector protected through ppb and dyb
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 33 advance information tected sector enables status polling and returns to read mode without having modified the contents of the protected sector. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing individual status read commands dyb status, ppb status, and ppb lock status to the device. password sector protection the password sector protection mode method allows an even higher level of se - curity than the persistent sector protection mode. there are two main differences between the persistent sector protection mode and the password sector protec - tion mode: ? when the device is first powered up, or comes out of a reset cycle, the ppb lock bit is set to the locked state , rather than cleared to the unlocked state. ? the only means to clear the ppb lock bit is by writing a unique 64-bit pass - word to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a one-time programmable (otp) region of the flash memory. once the password mode lock bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 1 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify commands. the password function works in conjunction with the password mode locking bit, which when set, pre - vents the password verify command from reading the contents of the password on the pins of the device. persistent protection bit lock (ppb lock bit) in password sector protection mode the persistent protection bit lock (ppb lock bit) is a volatile bit that reflects the state of the password mode lock bit after power-up reset. if the password mode lock bit is also set, after a hardware reset (reset# asserted) or a power-up re - set, the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. successful execution of the password unlock command to enter the entire password clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset# or taking the device through a power-on reset, resets the ppb lock bit to a ?1?. if the password mode lock bit is not set (device is operating in the default per - sistent protection mode). the password unlock command is ignored in persistent sector protection mode.
34 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information lock register the lock register consists of 4 bits. the customer secsi sector protection bit is dq0, persistent protection mode lock bit is dq1, password protection mode lock bit is dq2, and persistent sector protection otp bit is dq3. each of these bits are non-volatile. dq15-dq4 are reserved and will be 1?s. hardware data protection mode the device offers two types of data protection at the sector level: ? when wp# is at v il , the four outermost sectors are locked (device specific). ? when acc is at v il , all sectors are locked. the write protect pin (wp#) adds a final level of hardware program and erase protection to the outermost boot sectors. the outermost boot sectors are the sec - tors containing both the lower and upper set of outermost sectors in a dual-boot- configured device. when this pin is low it is not possible to change the con - tents of these outermost sectors. these sectors generally hold system boot code. so, the wp# pin can prevent any changes to the boot code that could over - ride the choices made while setting up sector protection during system initialization. the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. write protect (wp#) the write protect feature provides a hardware method of protecting the four out - ermost sectors. this function is provided by the wp# pin and overrides the previously discussed sector protection/unprotection method. if the system asserts v il on the wp# pin, the device disables program and erase functions in the ?outermost? boot sectors. the outermost boot sectors are the sectors containing both the lower and upper set of sectors in a dual-boot-config - ured device. if the system asserts v ih on the wp# pin, the device reverts to whether the boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp# pin must not be left floating or unconnected; inconsistent be - havior of the device may result. the wp # pin must be held stable during a command sequence execution. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro - tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the sys - tem must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . ta b l e 6 . lock register dq15-3 dq2 dq1 dq0 1?s password protection mode lock bit persistent protection mode lock bit customer secsi sector protection bit
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 35 advance information write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac - tive current until the operation is completed. i cc3 in ?dc characteristics? represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. while in asynchronous mode, the device automatically enables this mode when addresses remain stable for t acc + 20 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. st andard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. while in synchronous mode, the au - tomatic sleep mode is disabled. note that a new burst operation is required to provide new data. i cc6 in ?dc characteristics? represents the automatic sleep mode current specification. reset#: hardware reset input the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device im - mediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the de - vice is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of th e reset# pulse. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current will be greater.
36 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information reset# may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase operation, the device requires a time of t rp +t rp (during embedded algorithms) before the device is ready to read data again. if reset# is asserted when a program or erase operation is not executing, the reset operation is completed within a time of t rp (not during em - bedded algorithms). the system can read data t rh after reset# returns to v ih . refer to the " hardware reset (reset#) " section for reset# parameters and to figure 20 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. secsi? (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides an extra flash memory re - gion that enables permanent part identification through an electronic serial number (esn). the secsi sector is 256 words in length. all reads outside of the 256 word address range will return non-valid data. the factory indicator bit (dq7) is used to indicate whether or not the factory secsi sector is locked when shipped from the factory. the customer indicator bit (dq6) is used to indicate whether or not the customer secsi sector is locked when shipped from the fac - tory. the factory secsi bits are permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the secu - rity of the esn and customer code once the product is shipped to the field. the factory portion of the secsi sector is locked when shipped and the customer secsi sector that is either locked or is lockable. the factory secsi sector is al - ways protected when shipped from the factory, and has the factory indicator bit (dq7) permanently set to a ?1?. the customer secsi sector is typically shipped unprotected, allowing customers to utilize that sector in any manner they choose. the customer indicator bit set to ?0.? once the customer secsi sector area is protected, the customer indicator bit will be permanently set to ?1.? the system accesses the secsi sector through a command sequence (see the " enter secsi? sector/exit secsi sector command sequence " section ). after the system has written the enter secsi sector command sequence, it may read the secsi sector by using the addresses normally occupied by the memory array. this mode of operation continues until the system issues the exit secsi sector com - mand sequence, or until power is removed from the device. while secsi sector access is enabled, memory array read access, program operations, and erase op - erations to all sectors other than sa0 are also available. on power-up, or following a hardware reset, the device reverts to sending commands to the nor - mal address space. factory locked: factor secsi sector programmed and protected at the factory in a factory sector locked device, the factory secsi sector is protected when the device is shipped from the factory. the factory secsi sector cannot be modified in any way. the device is pre programmed with both a random number and a se - cure esn. the factory secsi sector is located at addresses 000000h?00007fh. the device is available pre programmed with one of the following:
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 37 advance information ? a random, secure esn only within the factor secsi sector ? customer code within the customer secsi sector through the spansion tm pro - gramming service ? both a random, secure esn and customer code through the spansion tm pro - gramming service. customers may opt to have their code programmed by spansion through the spansion tm programming services. spansion programs the customer?s code, with or without the random esn. the devices are then shipped from spansion?s factory with the factory secsi sector and customer secsi sector permanently locked. contact your local representative for details on using spansion tm programming services. customer secsi sector if the security feature is not required, the customer secsi sector can be treated as an additional flash memory space. the customer secsi sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock bypass functions are not avail - able when programming the customer secsi sector, but reading in banks 1 through 15 is available. the customer secsi sector is located at addresses 000080h?0000ffh. the customer secsi sector area can be protected by writing the secsi sector protection bit lock command sequence. once the customer secsi sector is locked and verified, the system must write the exit secsi sector region command sequence to return to reading and writing the remainder of the array. the customer secsi sector lock must be used with caution since, once locked, there is no procedure available for unlocking the customer secsi sector area and none of the bits in the customer secsi sector memory space can be modified in any way. secsi sector protection bit the customer secsi sector protection bit prevents programming of the customer secsi sector memory area. once set, the customer secsi sector memory area contents are non-modifiable. common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft - ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back - ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address (ba)555h any time the device is ready to read array data. the system can read cfi information at the addresses given in ta b l e 8 ta b l e 7 . secsi tm sector addresses sector sector size address range customer 128 words 000080h-0000ffh factory 128 words 000000h-00007fh
38 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information through ta b l e 1 1 within that bank. all reads outside of the cfi address range, within the bank, will return non-valid data. reads from other banks are allowed, writes are not. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au - toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in ta b l e 8 through ta b l e 1 1 . the system must write the reset command to return the device to the autoselect mode. for further information, please refer to the cfi specification and cfi publication 100. please contact your sales office for copies of these documents. not supported due to page programming requirement ta b l e 8 . cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) ta b l e 9 . system interface string addresses data description 1bh 0017h v cc min. (write/erase) dq7?dq4: volt, dq3?dq0: 100 millivolt 1ch 0019h v cc max. (write/erase) dq7?dq4: volt, dq3?dq0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0005h typical timeout per single byte/word write 2 n s (note ) 20h 0009h typical timeout for min. size buffer write 2 n s (00h = not supported) (note ) 21h 0008h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0003h max. timeout for byte/word write 2 n times typical (note ) 24h 0001h max. timeout for buffer write 2 n times typical (note ) 25h 0003h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 39 advance information ta b l e 1 0 . device geometry definition addresses data description 27h 0019h (ws256n) device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0005h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0003h 0000h 0080h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 00fdh (ws256n) erase block region 2 information 32h 33h 34h 0000h 0000h 0002h 35h 36h 37h 38h 0003h 0000h 0080h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information ta b l e 1 1 . primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0034h minor version number, ascii 45h 0010h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon technology (bits 5-2) 0011 = 0.13 m 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0008h sector protect/unprotect scheme 08 = advanced sector protection 4ah 00dfh (ws256n) simultaneous operation number of sectors in all banks except boot bank
40 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page, 04 = 16 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, dq7-dq4: volt, dq3-dq0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, dq7-dq4: volt, dq3-dq0: 100 mv 4fh 0001h top/bottom boot sector flag 0001h = dual boot device 50h 0001h program suspend. 00h = not supported 51h 0001h unlock bypass 00 = not supported, 01=supported 52h 0007h secsi sector (customer otp area) size 2 n bytes 53h 0014h hardware reset low time-out during an embedded algorithm to read mode maximum 2 n ns 54h 0014h hardware reset low time-out not during an embedded algorithm to read mode maximum 2 n ns 55h 0005h erase suspend time-out maximum 2 n ns 56h 0005h program suspend time-out maximum 2 n ns 57h 0010h bank organization: x = number of banks 58h 0013h (ws256n) bank 0 region information. x = number of sectors in bank 59h 0010h (ws256n) bank 1 region information. x = number of sectors in bank 5ah 0010h (ws256n) bank 2 region information. x = number of sectors in bank 5bh 0010h (ws256n) bank 3 region information. x = number of sectors in bank 5ch 0010h (ws256n) bank 4 region information. x = number of sectors in bank 5dh 0010h (ws256n) bank 5 region information. x = number of sectors in bank 5eh 0010h (ws256n) bank 6 region information. x = number of sectors in bank 5fh 0010h (ws256n) bank 7 region information. x = number of sectors in bank 60h 0010h (ws256n) bank 8 region information. x = number of sectors in bank 61h 0010h (ws256n) bank 9 region information. x = number of sectors in bank 62h 0010h (ws256n) bank 10 region information. x = number of sectors in bank 63h 0010h (ws256n) bank 11 region information. x = number of sectors in bank 64h 0010h (ws256n) bank 12 region information. x = number of sectors in bank 65h 0010h (ws256n) bank 13 region information. x = number of sectors in bank 66h 0010h (ws256n) bank 14 region information. x = number of sectors in bank 67h 0013h (ws256n) bank 15 region information. x = number of sectors in bank table 11. primary vendor-specific extended query (continued) addresses data description
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 41 advance information table 12. sector address / memory address map for the ws256n bank sector sector size a23?a14 (x16) address range bank 0 sa0 16 kwords 0000000000 000000h-003fffh sa1 16 kwords 0000000001 004000h-007fffh sa2 16 kwords 0000000010 008000h-00bfffh sa3 16 kwords 0000000011 00c000h-00ffffh sa4 64 kwords 00000001xx 010000h-01ffffh sa5 64 kwords 00000010xx 020000h-02ffffh sa6 64 kwords 00000011xx 030000h-03ffffh sa7 64 kwords 00000100xx 040000h-04ffffh sa8 64 kwords 00000101xx 050000h-05ffffh sa9 64 kwords 00000110xx 060000h-06ffffh sa10 64 kwords 00000111xx 070000h-07ffffh sa11 64 kwords 00001000xx 080000h-08ffffh sa12 64 kwords 00001001xx 090000h-09ffffh sa13 64 kwords 00001010xx 0a0000h-0affffh sa14 64 kwords 00001011xx 0b0000h-0bffffh sa15 64 kwords 00001100xx 0c0000h-0cffffh sa16 64 kwords 00001101xx 0d0000h-0dffffh sa17 64 kwords 00001110xx 0e0000h-0effffh sa18 64 kwords 00001111xx 0f0000h-0fffffh bank 1 sa19 64 kwords 00010000xx 100000h-10ffffh sa20 64 kwords 00010001xx 110000h-11ffffh sa21 64 kwords 00010010xx 120000h-12ffffh sa22 64 kwords 00010011xx 130000h-13ffffh sa23 64 kwords 00010100xx 140000h-14ffffh sa24 64 kwords 00010101xx 150000h-15ffffh sa25 64 kwords 00010110xx 160000h-16ffffh sa26 64 kwords 00010111xx 170000h-17ffffh sa27 64 kwords 00011000xx 180000h-18ffffh sa28 64 kwords 00011001xx 190000h-19ffffh sa29 64 kwords 00011010xx 1a0000h-1affffh sa30 64 kwords 00011011xx 1b0000h-1bffffh sa31 64 kwords 00011100xx 1c0000h-1cffffh sa32 64 kwords 00011101xx 1d0000h-1dffffh sa33 64 kwords 00011110xx 1e0000h-1effffh sa34 64 kwords 00011111xx 1f0000h-1fffffh
42 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information bank 2 sa35 64 kwords 00100000xx 200000h-20ffffh sa36 64 kwords 00100001xx 210000h-21ffffh sa37 64 kwords 00100010xx 220000h-22ffffh sa38 64 kwords 00100011xx 230000h-23ffffh sa39 64 kwords 00100100xx 240000h-24ffffh sa40 64 kwords 00100101xx 250000h-25ffffh sa41 64 kwords 00100110xx 260000h-26ffffh sa42 64 kwords 00100111xx 270000h-27ffffh sa43 64 kwords 00101000xx 280000h-28ffffh sa44 64 kwords 00101001xx 290000h-29ffffh sa45 64 kwords 00101010xx 2a0000h-2affffh sa46 64 kwords 00101011xx 2b0000h-2bffffh sa47 64 kwords 00101100xx 2c0000h-2cffffh sa48 64 kwords 00101101xx 2d0000h-2dffffh sa49 64 kwords 00101110xx 2e0000h-2effffh sa50 64 kwords 00101111xx 2f0000h-2fffffh bank 3 sa51 64 kwords 00110000xx 300000h-30ffffh sa52 64 kwords 00110001xx 310000h-31ffffh sa53 64 kwords 00110010xx 320000h-32ffffh sa54 64 kwords 00110011xx 330000h-33ffffh sa55 64 kwords 00110100xx 340000h-34ffffh sa56 64 kwords 00110101xx 350000h-35ffffh sa57 64 kwords 00110110xx 360000h-36ffffh sa58 64 kwords 00110111xx 370000h-37ffffh sa59 64 kwords 00111000xx 380000h-38ffffh sa60 64 kwords 00111001xx 390000h-39ffffh sa61 64 kwords 00111010xx 3a0000h-3affffh sa62 64 kwords 00111011xx 3b0000h-3bffffh sa63 64 kwords 00111100xx 3c0000h-3cffffh sa64 64 kwords 00111101xx 3d0000h-3dffffh sa65 64 kwords 00111110xx 3e0000h-3effffh sa66 64 kwords 00111111xx 3f0000h-3fffffh table 12. sector address / memory address map for the ws256n (continued) bank sector sector size a23?a14 (x16) address range
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 43 advance information bank 4 sa67 64 kwords 01000000xx 400000h-40ffffh sa68 64 kwords 01000001xx 410000h-41ffffh sa69 64 kwords 01000010xx 420000h-42ffffh sa70 64 kwords 01000011xx 430000h-43ffffh sa71 64 kwords 01000100xx 440000h-44ffffh sa72 64 kwords 01000101xx 450000h-45ffffh sa73 64 kwords 01000110xx 460000h-46ffffh sa74 64 kwords 01000111xx 470000h-47ffffh sa75 64 kwords 01001000xx 480000h-48ffffh sa76 64 kwords 01001001xx 490000h-49ffffh sa77 64 kwords 01001010xx 4a0000h-4affffh sa78 64 kwords 01001011xx 4b0000h-4bffffh sa79 64 kwords 01001100xx 4c0000h-4cffffh sa80 64 kwords 01001101xx 4d0000h-4dffffh sa81 64 kwords 01001110xx 4e0000h-4effffh sa82 64 kwords 01001111xx 4f0000h-4fffffh bank 5 sa83 64 kwords 01010000xx 500000h-50ffffh sa84 64 kwords 01010001xx 510000h-51ffffh sa85 64 kwords 01010010xx 520000h-52ffffh sa86 64 kwords 01010011xx 530000h-53ffffh sa87 64 kwords 01010100xx 540000h-54ffffh sa88 64 kwords 01010101xx 550000h-55ffffh sa89 64 kwords 01010110xx 560000h-56ffffh sa90 64 kwords 01010111xx 570000h-57ffffh sa91 64 kwords 01011000xx 580000h-58ffffh sa92 64 kwords 01011001xx 590000h-59ffffh sa93 64 kwords 01011010xx 5a0000h-5affffh sa94 64 kwords 01011011xx 5b0000h-5bffffh sa95 64 kwords 01011100xx 5c0000h-5cffffh sa96 64 kwords 01011101xx 5d0000h-5dffffh sa97 64 kwords 01011110xx 5e0000h-5effffh sa98 64 kwords 01011111xx 5f0000h-5fffffh table 12. sector address / memory address map for the ws256n (continued) bank sector sector size a23?a14 (x16) address range
44 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information bank 6 sa99 64 kwords 01100000xx 600000h-60ffffh sa100 64 kwords 01100001xx 610000h-61ffffh sa101 64 kwords 01100010xx 620000h-62ffffh sa102 64 kwords 01100011xx 630000h-63ffffh sa103 64 kwords 01100100xx 640000h-64ffffh sa104 64 kwords 01100101xx 650000h-65ffffh sa105 64 kwords 01100110xx 660000h-66ffffh sa106 64 kwords 01100111xx 670000h-67ffffh sa107 64 kwords 01101000xx 680000h-68ffffh sa108 64 kwords 01101001xx 690000h-69ffffh sa109 64 kwords 01101010xx 6a0000h-6affffh sa110 64 kwords 01101011xx 6b0000h-6bffffh sa111 64 kwords 01101100xx 6c0000h-6cffffh sa112 64 kwords 01101101xx 6d0000h-6dffffh sa113 64 kwords 01101110xx 6e0000h-6effffh sa114 64 kwords 01101111xx 6f0000h-6fffffh bank 7 sa115 64 kwords 01110000xx 700000h-70ffffh sa116 64 kwords 01110001xx 710000h-71ffffh sa117 64 kwords 01110010xx 720000h-72ffffh sa118 64 kwords 01110011xx 730000h-73ffffh sa119 64 kwords 01110100xx 740000h-74ffffh sa120 64 kwords 01110101xx 750000h-75ffffh sa121 64 kwords 01110110xx 760000h-76ffffh sa122 64 kwords 01110111xx 770000h-77ffffh sa123 64 kwords 01111000xx 780000h-78ffffh sa124 64 kwords 01111001xx 790000h-79ffffh sa125 64 kwords 01111010xx 7a0000h-7affffh sa126 64 kwords 01111011xx 7b0000h-7bffffh sa127 64 kwords 01111100xx 7c0000h-7cffffh sa128 64 kwords 01111101xx 7d0000h-7dffffh sa129 64 kwords 01111110xx 7e0000h-7effffh sa130 64 kwords 01111111xx 7f0000h-7fffffh table 12. sector address / memory address map for the ws256n (continued) bank sector sector size a23?a14 (x16) address range
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 45 advance information bank 8 sa131 64 kwords 10000000xx 800000h-80ffffh sa132 64 kwords 10000001xx 810000h-81ffffh sa133 64 kwords 10000010xx 820000h-82ffffh sa134 64 kwords 10000011xx 830000h-83ffffh sa135 64 kwords 10000100xx 840000h-84ffffh sa136 64 kwords 10000101xx 850000h-85ffffh sa137 64 kwords 10000110xx 860000h-86ffffh sa138 64 kwords 10000111xx 870000h-87ffffh sa139 64 kwords 10001000xx 880000h-88ffffh sa140 64 kwords 10001001xx 890000h-89ffffh sa141 64 kwords 10001010xx 8a0000h-8affffh sa142 64 kwords 10001011xx 8b0000h-8bffffh sa143 64 kwords 10001100xx 8c0000h-8cffffh sa144 64 kwords 10001101xx 8d0000h-8dffffh sa145 64 kwords 10001110xx 8e0000h-8effffh sa146 64 kwords 10001111xx 8f0000h-8fffffh bank 9 sa147 64 kwords 10010000xx 900000h-90ffffh sa148 64 kwords 10010001xx 910000h-91ffffh sa149 64 kwords 10010010xx 920000h-92ffffh sa150 64 kwords 10010011xx 930000h-93ffffh sa151 64 kwords 10010100xx 940000h-94ffffh sa152 64 kwords 10010101xx 950000h-95ffffh sa153 64 kwords 10010110xx 960000h-96ffffh sa154 64 kwords 10010111xx 970000h-97ffffh sa155 64 kwords 10011000xx 980000h-98ffffh sa156 64 kwords 10011001xx 990000h-99ffffh sa157 64 kwords 10011010xx 9a0000h-9affffh sa158 64 kwords 10011011xx 9b0000h-9bffffh sa159 64 kwords 10011100xx 9c0000h-9cffffh sa160 64 kwords 10011101xx 9d0000h-9dffffh sa161 64 kwords 10011110xx 9e0000h-9effffh sa162 64 kwords 10011111xx 9f0000h-9fffffh table 12. sector address / memory address map for the ws256n (continued) bank sector sector size a23?a14 (x16) address range
46 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information bank 10 sa163 64 kwords 10100000xx a00000h-a0ffffh sa164 64 kwords 10100001xx a10000h-a1ffffh sa165 64 kwords 10100010xx a20000h-a2ffffh sa166 64 kwords 10100011xx a30000h-a3ffffh sa167 64 kwords 10100100xx a40000h-a4ffffh sa168 64 kwords 10100101xx a50000h-a5ffffh sa169 64 kwords 10100110xx a60000h-a6ffffh sa170 64 kwords 10100111xx a70000h-a7ffffh sa171 64 kwords 10101000xx a80000h-a8ffffh sa172 64 kwords 10101001xx a90000h-a9ffffh sa173 64 kwords 10101010xx aa0000h-aaffffh sa174 64 kwords 10101011xx ab0000h-abffffh sa175 64 kwords 10101100xx ac0000h-acffffh sa176 64 kwords 10101101xx ad0000h-adffffh sa177 64 kwords 10101110xx ae0000h-aeffffh sa178 64 kwords 10101111xx af0000h-afffffh bank 11 sa179 64 kwords 10110000xx b00000h-b0ffffh sa180 64 kwords 10110001xx b10000h-b1ffffh sa181 64 kwords 10110010xx b20000h-b2ffffh sa182 64 kwords 10110011xx b30000h-b3ffffh sa183 64 kwords 10110100xx b40000h-b4ffffh sa184 64 kwords 10110101xx b50000h-b5ffffh sa185 64 kwords 10110110xx b60000h-b6ffffh sa186 64 kwords 10110111xx b70000h-b7ffffh sa187 64 kwords 10111000xx b80000h-b8ffffh sa188 64 kwords 10111001xx b90000h-b9ffffh sa189 64 kwords 10111010xx ba0000h-baffffh sa190 64 kwords 10111011xx bb0000h-bbffffh sa191 64 kwords 10111100xx bc0000h-bcffffh sa192 64 kwords 10111101xx bd0000h-bdffffh sa193 64 kwords 10111110xx be0000h-beffffh sa194 64 kwords 10111111xx bf0000h-bfffffh table 12. sector address / memory address map for the ws256n (continued) bank sector sector size a23?a14 (x16) address range
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 47 advance information bank 12 sa195 64 kwords 11000000xx c00000h-c0ffffh sa196 64 kwords 11000001xx c10000h-c1ffffh sa197 64 kwords 11000010xx c20000h-c2ffffh sa198 64 kwords 11000011xx c30000h-c3ffffh sa199 64 kwords 11000100xx c40000h-c4ffffh sa200 64 kwords 11000101xx c50000h-c5ffffh sa201 64 kwords 11000110xx c60000h-c6ffffh sa202 64 kwords 11000111xx c70000h-c7ffffh sa203 64 kwords 11001000xx c80000h-c8ffffh sa204 64 kwords 11001001xx c90000h-c9ffffh sa205 64 kwords 11001010xx ca0000h-caffffh sa206 64 kwords 11001011xx cb0000h-cbffffh sa207 64 kwords 11001100xx cc0000h-ccffffh sa208 64 kwords 11001101xx cd0000h-cdffffh sa209 64 kwords 11001110xx ce0000h-ceffffh sa210 64 kwords 11001111xx cf0000h-cfffffh bank 13 sa211 64 kwords 11010000xx d00000h-d0ffffh sa212 64 kwords 11010001xx d10000h-d1ffffh sa213 64 kwords 11010010xx d20000h-d2ffffh sa214 64 kwords 11010011xx d30000h-d3ffffh sa215 64 kwords 11010100xx d40000h-d4ffffh sa216 64 kwords 11010101xx d50000h-d5ffffh sa217 64 kwords 11010110xx d60000h-d6ffffh sa218 64 kwords 11010111xx d70000h-d7ffffh sa219 64 kwords 11011000xx d80000h-d8ffffh sa220 64 kwords 11011001xx d90000h-d9ffffh sa221 64 kwords 11011010xx da0000h-daffffh sa222 64 kwords 11011011xx db0000h-dbffffh sa223 64 kwords 11011100xx dc0000h-dcffffh sa224 64 kwords 11011101xx dd0000h-ddffffh sa225 64 kwords 11011110xx de0000h-deffffh sa226 64 kwords 11011111xx df0000h-dfffffh table 12. sector address / memory address map for the ws256n (continued) bank sector sector size a23?a14 (x16) address range
48 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information bank 14 sa227 64 kwords 11100000xx e00000h-e0ffffh sa228 64 kwords 11100001xx e10000h-e1ffffh sa229 64 kwords 11100010xx e20000h-e2ffffh sa230 64 kwords 11100011xx e30000h-e3ffffh sa231 64 kwords 11100100xx e40000h-e4ffffh sa232 64 kwords 11100101xx e50000h-e5ffffh sa233 64 kwords 11100110xx e60000h-e6ffffh sa234 64 kwords 11100111xx e70000h-e7ffffh sa235 64 kwords 11101000xx e80000h-e8ffffh sa236 64 kwords 11101001xx e90000h-e9ffffh sa237 64 kwords 11101010xx ea0000h-eaffffh sa238 64 kwords 11101011xx eb0000h-ebffffh sa239 64 kwords 11101100xx ec0000h-ecffffh sa240 64 kwords 11101101xx ed0000h-edffffh sa241 64 kwords 11101110xx ee0000h-eeffffh sa242 64 kwords 11101111xx ef0000h-efffffh bank 15 sa243 64 kwords 11110000xx f00000h-f0ffffh sa244 64 kwords 11110001xx f10000h-f1ffffh sa245 64 kwords 11110010xx f20000h-f2ffffh sa246 64 kwords 11110011xx f30000h-f3ffffh sa247 64 kwords 11110100xx f40000h-f4ffffh sa248 64 kwords 11110101xx f50000h-f5ffffh sa249 64 kwords 11110110xx f60000h-f6ffffh sa250 64 kwords 11110111xx f70000h-f7ffffh sa251 64 kwords 11111000xx f80000h-f8ffffh sa252 64 kwords 11111001xx f90000h-f9ffffh sa253 64 kwords 11111010xx fa0000h-faffffh sa254 64 kwords 11111011xx fb0000h-fbffffh sa255 64 kwords 11111100xx fc0000h-fcffffh sa256 64 kwords 11111101xx fd0000h-fdffffh sa257 64 kwords 11111110xx fe0000h-feffffh sa258 16 kwords 1111111100 ff0000h-ff3fffh sa259 16 kwords 1111111101 ff4000h-ff7fffh sa260 16 kwords 1111111110 ff8000h-ffbfffh sa261 16 kwords 1111111111 ffc000h-ffffffh table 12. sector address / memory address map for the ws256n (continued) bank sector sector size a23?a14 (x16) address range
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 49 advance information command definitions writing specific address and data commands or sequences into the command register initiates device operations. the " command definition summary " section defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. refer to ?ac characteristics?synchronous? and ?ac char - acteristics?asynchronous? for timing diagrams. reading array data the device is automatically set to reading asynchronous array data after device power-up. no commands are required to retrieve data in asynchronous mode. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. after completing a pro - gramming operation in the erase suspend mode, the system may once again read array data from any non-erase-suspended sector within the same bank. see the " erase suspend/erase resume commands " section for more information. after the device accepts a program suspend command, the corresponding bank enters the program-suspend-read mode, after which the system can read data from any non-program-suspended sector within the same bank. see the " pro - gram suspend/program resume commands " section for more information. the system must issue the reset command to return a bank to the read (or erase- suspend-read) mode if dq5 goes high during an active program or erase opera - tion, or if the bank is in the autoselect mode. see the " reset command " section for more information. if dq1 goes high during write buffer programming, the system must issue the write buffer abort reset command. see also " requirements for asynchronous read operation (non-burst) " section and " requirements for synchronous (burst) read operation " section for more in - formation. the asynchronous read and synchronous/burst read tables provide the read parameters, and figure 13 , figure 14 , and figure 18 show the timings. set configuration register command sequence the device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, rdy configuration, and synchronous mode active (see figure 16 for details). the configuration reg - ister must be set before the device will enter burst mode. on power up or reset, the device is set in asynchronous read mode and the configuration register is re - set. the configuration register is not reset after deasserting ce#. the configuration register is loaded with a four-cycle command sequence. the first two cycles are standard unlock sequences. on the third cycle, the data should be d0h and address bits should be 555h. during the fourth cycle, the con - figuration code should be entered onto the data bus with the address bus set to address 000h. once the data has been programmed into the configuration regis - ter, a software reset command is required to set the device into the correct state. the device will power up or after a hardware reset with the default setting, which is in asynchronous mode. the register must be set before the device can enter
50 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information synchronous mode. the configuration register can not be changed during device operations (program, erase, or sector lock). read configuration regi ster command sequence the configuration register can be read with a four-cycle command sequence. the first two cycles are standard unlock sequences. on the third cycle, the data should be c6h and address bits should be 555h. during the fourth cycle, the con - figuration code should be read out of the data bus with the address bus set to address 000h. once the data has been read from the configuration register, a software reset command is required to set the device into the correct state. read mode setting this setting allows the system to enable or disable burst mode during system op - erations. configuration bit cr15 determines this setting: ?1? for asynchronous mode, ?0? for synchronous mode. programmable wait state configuration the programmable wait state feature informs the device of the number of clock cycles that must elapse after avd# is driven active before data will be available. this value is determined by the input frequency of the device. configuration bit cr13?cr11 determine the setting (see ta b l e 1 3 ). the wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. the number of wait states that should be programmed into the device is directly related to the clock frequency. figure 1. synchronous/asynchronous state diagram power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (d15 = 0) set burst mode configuration register command for asynchronous mode (d15 = 1)
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 51 advance information it is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. a hardware reset will set the wait state to the default setting. programmable wait state if the device is equipped with the handshaking option, the host system should set cr13-cr11 to 010 for a clock frequency of 54 mhz or to 011 for a clock fre - quency of 66 mhz for the system/device to execute at maximum speed. ta b l e 1 4 describes the typical number of clock cycles (wait states) for various conditions. boundary crossing latency if the device is operating above 66 mhz, an additional wait state must be inserted to account for boundary crossing latency. this is done by setting cr14 to a ?1? (default). if the device is operating at or below 66 mhz, the additional wait state for boundary crossing is not needed. therefore the cr14 can be changed to a ?0? to remove boundary crossing latency. set internal clock frequency the device switches at the full frequency of the external clock up to 66 mhz when cr9 is set to a ?1? (default). handshaking for optimal burst mode performance, the host system must set the appropriate number of wait states in the flash device depending on the clock frequency. the autoselect function allows the host system to determine whether the flash device is enabled for handshaking. see the " autoselect command sequence " sec - tion for more information. ta b l e 1 3 . programmable wait state settings cr13 cr12 cr11 total initial access cycles 0 0 0 2 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 7 (default) 1 1 0 reserved 1 1 1 reserved notes: 1. upon power-up or hardware reset, th e default setting is seven wait states. 2. rdy will default to being active with data when the wait state setting is set to a total initial access cycle of 2. ta b l e 1 4 . wait states for handshaking conditions at address typical no. of clock cycles after avd# low 54 mhz 66 mhz initial address (v io = 1.8 v) 4 5
52 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information burst sequence only sequential burst is allowed in the device. cr7 defaults to a ?1? and must al - ways be set to a ?1?. burst length configuration the device supports four different read modes: continuous mode, and 8, 16, and 32 word linear with or without wrap around modes. a continuous sequence (de - fault) begins at the starting address and advances the address pointer until the burst operation is complete. if the highest address in the device is reached during the continuous burst read mode, the address pointer wraps around to the lowest address. for example, an eight-word linear read with wrap around begins on the starting address written to the device and then advances to the next 8 word boundary. the address pointer then returns to the 1st word after the previous eight word boundary, wrapping through the starting location. the sixteen- and thirty-two lin - ear wrap around modes operate in a fashion similar to the eight-word mode. ta b l e 1 5 shows the cr2-cr0 and settings for the four read modes. burst wrap around by default, the device will perform burst wrap around with cr3 set to a ?1?. changing the cr3 to a ?0? disables burst wrap around. burst active clock edge configuration by default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. subsequent outputs will also be on the following rising edges, barring any delays. the device can be set so that the falling clock edge is active for all synchronous accesses. cr6 determines this setting; ?1? for rising active (default), ?0? for falling active. rdy configuration by default, the device is set so that the rdy pin will output v oh whenever there is valid data on the outputs. the device can be set so that rdy goes active one data cycle before active data. cr8 determines this setting; ?1? for rdy active (default) with data, ?0? for rdy active one clock cycle before valid data. in asyn - chronous mode, rdy is an open-drain output. rdy polarity by default, the rdy pin will always indicate that the device is ready to handle a new transaction with cr10 set to a ?1? when high. in this case, the rdy pin is active high. changing the cr10 to a ?0? sets the rdy pin to be active low. in this ta b l e 1 5 . burst length configuration burst modes address bits cr2 cr1 cr0 continuous 0 0 0 8-word linear 0 1 0 16-word linear 0 1 1 32-word linear 1 0 0 note: upon power-up or hardware reset the default setting is continuous.
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 53 advance information case, the rdy pin will always indicate that the device is ready to handle a new transaction when low. configuration register ta b l e 1 6 shows the address bits that determine the configuration register settings for various device functions. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys - tem was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. ta b l e 1 6 . configuration register cr bit function settings (binary) cr15 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous mode (default) cr14 boundary crossing 0 = no extra boundary crossing latency 1 = with extra boundary crossing latency (default) cr13 programmable wait state 000 = data is valid on the 2nd active clk edge after addresses are latched 001 = data is valid on the 3rd active clk edge after addresses are latched 010 = data is valid on the 4th active clk edge after addresses are latched 011 = data is valid on the 5th active clk edge after addresses are latched 100 = data is valid on the 6th active clk edge after addresses are latched 101 = data is valid on the 7th active clk edge after addresses are latched (default) 110 = reserved 111 = reserved cr12 cr11 cr10 rdy polarity 0 = rdy signal is active low 1 = rdy signal is active high (default) cr9 set internal clock frequency 0 = reserved for future use 1 = internal clock switches at full frequency of the external clock (default) cr8 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) cr7 burst sequence 0 = reserved for future use 1 = sequential burst order (default) cr6 clock 0 = burst starts and data is output on the falling edge of clk 1 = burst starts and data is output on the rising edge of clk (default) cr3 burst wrap around 0 = no wrap around burst 1 = wrap around burst (default) cr2 burst length 000 = continuous (default) 010 = 8-word linear burst 011 = 16-word linear burst 100 = 32-word linear burst (all other bit settings are reserved) cr1 cr0 notes: device will be in the default state upon power-up or hardware reset.
54 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information the reset command may be written between the sequence cycles in a program command sequence before program ming begins (prior to the third cycle). this re - sets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writ - ing the reset command returns that bank to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the op - eration is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend and program-suspend-read mode if that bank was in pro - gram suspend). note: if dq1 goes high during a write buffer programming operation, the system must write the ?write to buffer abort reset? command sequence to reset the device to reading array data. the standard reset command will not work. see table 17 for details on this command sequence. autoselect command sequence the autoselect command sequence allows the host system to access the manu - facturer and device codes, and determine whether or not a sector is protected. the " command definition summary " section shows the address and data re - quirements. the autoselect command sequence may be written to an address within a bank that is either in the re ad or erase-suspend-read mode. the autose - lect command may not be written while the device is actively programming or erasing in the other bank. autoselect does not support simultaneous operations nor synchronous mode. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au - toselect command. the bank then enters the autoselect mode. the system may read at any address within the same bank any number of times without initiating another autoselect command sequence. read commands to other banks will re - turn data from the array. writes to other banks is not allowed. the following table describes the address requirements for the various autoselect functions, and the resulting data. ba represents the bank address. the device id is read in three cycles. ta b l e 1 7 . autoselect addresses description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 55 advance information the system must write the reset command to return to the read mode (or erase- suspend-read mode if the bank was previously in erase suspend). enter secsi? sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing a random, eight word electronic serial number (esn). the system can access the secsi sector re - gion by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the device to normal operation. the secsi sector is not acces - sible when the device is executing an embedded program or embedded erase algorithm. the " command definition summary " section shows the address and data requirements for both command sequences. word program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com - mand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further con - trols or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. device id, word 2 (ba) + 0eh 2230 (ws256n) device id, word 3 (ba) + 0fh 2200 indicator bits (ba) + 03h dq15 - dq8 = 0 dq7 - factory lock bit 1 = locked, 0 = not locked dq6 -customer lock bit 1 = locked, 0 = not locked dq5 - handshake bit 1 = reserved, 0 = standard handshake dq4 & dq3 - wp# protection boot code 00 = wp# protects both top boot and bottom boot sectors, 01 = reserved, 10 = reserved 11 = reserved dq2 = 0 dq1 - dyb power up state (dq1 = lock register dq4) 1 = unlocked (user option) 0 = locked (default) dq0 - ppb eraseability (dq0 = lock register dq3) 1 = erase allowed 0 = erase disabled table 17. autoselect addresses description address read data
56 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information when the embedded program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7 or dq6. refer to the write op - eration status section for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that the secsi sector, autoselect, and cfi functions are unavailable when a program operation is in progress. note that a hard - ware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. program - ming to the same word address multiple times without intervening erases is limited. for such application requirements, please contact your local spansion representative. any word cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? write buffer programming command sequence write buffer programming sequence allows for faster programming compared to the standard program command sequence. write buffer programming allows the system to write 32 words in one programming operation. see the " write buffer programming operation " section for the program command sequence. ta b l e 1 8 . write buffer command sequence sequence address data comment unlock command 1 555 00aa not required in the unlock bypass mode unlock command 2 2aa 0055 same as above write buffer load starting address 0025h specify the number of program locations starting address word count number of locations to program minus 1 (must be 32 - 1 = 31) load 1st data word starting address program data all addresses must be within write-buffer-page boundaries, but do not have to be loaded in any order load next data word write buffer location program data same as above ... ... ... same as above load last data word write buffer location program data same as above write buffer program confirm sector address 0029h this command must follow the last write buffer location loaded, or the operation will abort device goes busy status monitoring through dq pins (perform data bar polling on the last loaded address )
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 57 advance information unlock bypass command sequence the unlock bypass feature allows faster programming than the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command se - figure 2. write buffer programming operation write ?write to buffer? command and sector address write number of addresses to program minus 1 (wc = 31) and sector address write program buffer to flash sector address write first address/data write to a different sector address fail or abort pass read dq15 - dq0 at last loaded address read dq15 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? part of ?write to buffer? command sequence yes yes yes yes yes yes no no no no no no abort write to buffer operation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode.
58 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information quence, resulting in faster total programming time. the host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. the erase command sequences are four cycles in length instead of six cycles. the " command definition summary " section shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the read, unlock bypass program, unlock bypass sector erase, unlock bypass chip erase, and unlock bypass reset com - mands are valid. to exit the unlock bypass mode, the system must issue the two- cycle unlock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. the device offers accelerated program operations through the acc input. when the system asserts v hh on this input, the device automatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the acc input to ac - celerate the operation. figure 3 illustrates the algorithm for the program operation. refer to the erase/ program operations table in ?ac characteristics?asynchronous? for parameters, and figure 21 for timing diagrams. chip erase command sequence chip erase is a six bus cycle operation or, in the unlock bypass mode, a four-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. tw o additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to note: see the " command definition summary " section for program command sequence. figure 3. program operation start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 59 advance information erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the " command definition summary " section shows the address and data require - ments for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to ?write operation sta - tus? for information on these status bits. any commands written during the chip er ase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. the command sequence is two cycles in length instead of six cycles. figure 4 illustrates the algorithm for the erase operation. refer to the " erase/pro - gram operations @ v io = 1.8 v " section for parameters and timing diagrams. sector erase command sequence sector erase is a six bus cycle operation or, in the unlock bypass mode, a four- cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then followed by the addr ess of the sector to be erased, and the sector erase command. the " command definition summary " section shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em - bedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than 50 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise era - sure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor inter - rupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. the system must rewrite the command se - quence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see the " dq3: sector erase timer " section .) the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading
60 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information dq7 or dq6/dq2 in the erasing bank. refer to ?write operation status? for in - formation on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im - mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. the command sequence is four cycles cycles in length instead of six cycles. figure 4 illustrates the algorithm for the erase operation. refer to the " erase/pro - gram operations @ v io = 1.8 v " section for parameters and timing diagrams. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase oper - ation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this com - mand is valid only during the sector erase operation, including the minimum 50 s time-out period during the sector erase command sequence. the erase sus - pend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. how - ever, when the erase suspend command is written during the sector erase time- out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-sus - pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta - tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to ta b l e 2 0 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. in the erase-suspend-read mode, the system can also issue the autoselect com - mand sequence. refer to the " write buffer programming operation " section and the " autoselect command sequence " section for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase- suspended bank is required when writ - ing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing.
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 61 advance information program suspend/program resume commands the program suspend command allows the system to interrupt an embedded programming operation or a ?write to buffer? programming operation so that data can read from any non-suspended sector. when the program suspend com - mand is written during a programming process, the device halts the programming operation within 20 s and updates the status bits. addresses are ?don?t-cares? when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secsi sector area, then user must use the proper command sequences to enter and exit this region. the system may also write the autoselect command sequence when the device is in program suspend mode. the device allows reading autoselect codes in the suspended sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to program suspend mode, and is ready for another valid operation. see ?autoselect command sequence? for more information. after the program resume command is written, the device reverts to program - ming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see ?write operation status? for more information. the system must write the program resume command (address bits are ?don?t care?) to exit the program suspend mode and continue the programming opera - tion. further writes of the program resume command are ignored. another notes: 1. see the " command definition summary " section for erase command sequence. 2. see the section on dq3 for information on the sector erase timer. figure 4. erase operation start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
62 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information program suspend command can be written after the device has resumed programming. lock register command set definitions the lock register command set permits the user to program the secsi sector protection bit, persistent protection mode lock bit, or password protection mode lock bit one time. the lock command set also allows for the reading of the secsi sector protection bit, persistent protection mode lock bit, or password protection mode lock bit. the lock register command set entry command sequence must be issued prior to any of the following commands to enable proper command execution. ? lock register program command ? lock register read command ? lock register exit command note that issuing the lock register command set entry command disables reads and writes for bank 0. reads from other banks excluding bank 0 are allowed. the lock register command set exit command must be issued after the ex - ecution of the commands to reset the device to read mode. otherwise the device will hang. for either the secsi sector to be locked, or the device to be permanently set to the persistent protection mode or the password protection mode, the sequence of a lock register command set exit command, must be initiated after issuing the secsi protection bit program , persistent protection mode locking bit program , or the password protection mode locking bit program com - mands. note that if the persistent protection mode locking bit and the password protection mode locking bit are programmed at the same time, neither will be programmed. note that issuing the lock register command set exit command re-enables reads and writes for bank 0. password protection command set definitions the password protection command set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. the password protection command set entry command sequence must be issued prior to any of the following commands to enable proper command execution. ? password program command ? password read command ? password unlock command note that issuing the password protection command set entry command disables reads and writes for bank 0. reads and writes for other banks excluding bank 0 are allowed. the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. there is no special addressing order required for programming the password.
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 63 advance information once the password is written and verified, the password mode locking bit must be set in order to prevent verification. the password program command is only capable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm? with the cell remaining as a ?0?. the password is all f?s when shipped from the factory. all 64- bit password combinations are valid as a password. the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is programmed and the user attempts to verify the password, the device will always drive all f?s onto the dq data bus. the lower two address bits (a1?a0) are valid during the password read, pass - word program, and password unlock. the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become accessible for modification. the exact password must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 1 s at a time to prevent a hacker from running through all the 64-bit combinations in an at - tempt to correctly match a password. if the command is issued before the 1 s execution window for each portion of the unlock, the command will be ignored. the password unlock function is accomplished by writing password unlock com - mand and data to the device to perform the clearing of the ppb lock bit. the password is 64 bits long. a1 and a0 are used for matching. writing the password unlock command does not need to be address order specific. an example se - quence is starting with the lower address a1?a0= 00, followed by a1?a0= 01, a1?a0= 10, and a1?a0= 11. approximately 1 sec is required for unlocking the device after the valid 64-bit password is given to the device. it is the responsibility of the microprocessor to keep track of the 64-bit password as it is entered with the password unlock com - mand, the order, and when to read the ppb lock bit to confirm successful password unlock. in order to re-lock the device into the password mode, the ppb lock bit set command can be re-issued. the password protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. otherwise the device will hang. note that issuing the password protection command set exit command re- enables reads and writes for bank 0. non-volatile sector protection command set definitions the non-volatile sector protection command set permits the user to program the persistent protection bits (ppbs), erase all of the persistent protection bits (ppbs), and read the logic state of the persistent protection bits (ppbs). the non-volatile sector protection command set entry command se - quence must be issued prior to any of the following commands to enable proper command execution. ? ppb program command ? all ppb erase command ? ppb status read command note that issuing the non-volatile sector protection command set entry command disables reads and writes for the bank selected. reads within that
64 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information bank, will return the ppb status for that sector. writes within that bank, will set the ppb for that sector. reads from other banks are allowed, writes are not al - lowed. all reads must be performed using the asynchronous mode. the ppb program command is used to program, or set, a given ppb. each ppb is individually programmed (but is bulk erased with the other ppbs). the specific sector address (a23?a14 ws256n) are written at the same time as the program command. if the ppb lock bit is set, the ppb program command will not execute and the command will time-out without programming the ppb. the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually erasing a specific ppb. unlike the ppb program, no specific sector address is required. however, when the ppb erase command is written, all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command will not execute and the command will time-out without erasing the ppbs. the device will preprogram all ppbs prior to erasing when issuing the all ppb erase command. also note that the total number of ppb program/erase cycles has the same endurance as the flash memory array. the programming state of the ppb for a given sector can be verified by writing a ppb status read command to the device. the non-volatile sector protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the non-volatile sector protection command set exit command re-enables reads and writes for bank 0. global volatile sector protection freeze command set the global volatile sector protection freeze command set permits the user to set the ppb lock bit and reading the logic state of the ppb lock bit. the volatile sector protection freeze command set entry command se - quence must be issued prior to any of the commands listed following to enable proper command execution. ? ppb lock bit set command ? ppb lock bit status read command reads from all banks are allowed. the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. once the ppb lock bit is set, it cannot be cleared unless the device is taken through a power-on clear (for persistent sector protec - tion mode) or the password unlock command is executed (for password sector protection mode). if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on reset cycle. the programming state of the ppb lock bit can be verified by executing a ppb lock bit status read command to the device. the global volatile sector protection freeze command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode.
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 65 advance information volatile sector protection command set the volatile sector protection command set permits the user to set the dynamic protection bit (dyb), clear the dynamic protection bit (dyb), and read the logic state of the dynamic protection bit (dyb). the volatile sector protection command set entry command sequence must be issued prior to any of the following commands to enable proper com - mand execution. ? dyb set command ? dyb clear command ? dyb status read command note that issuing the volatile sector protection command set entry com - mand disables reads and writes for the bank selected with the command. reads within that bank, will return the dyb status for that sector. writes within that bank, will set the dyb for that sector. reads for other banks excluding that bank are allowed, writes are not allowed. all reads must be performed using the asyn - chronous mode. the dyb set/clear command is used to set or clear a dyb for a given sector. the high order address bits (a23?a14 for the ws256n) are issued at the same time as the code 00h or 01h on dq7-dq0. all other dq data bus pins are ignored dur - ing the data write cycle. the dybs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. the dybs are cleared at power-up or hardware reset. the programming state of the dyb for a given sector can be verified by writing a dyb status read command to the device. the volatile sector protection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the volatile sector protection command set exit command re-enables reads and writes for bank 0. secsi sector entry command the secsi sector entry command allows the following commands to be executed ? read from secsi sector ? program to secsi sector sector 0 is remapped from memory array to secsi sector array. reads can be performed using the asynchronous or synchronous mode. burst mode reads within secsi sector will wrap from address ffh back to address 00h. reads out - side of sector 0 will return memory array data. continuous burst read past the maximum address is undefined. simultaneous operations are allowed except for bank 0. once the secsi sector entry command is issued, the secsi sector exit command has to be issued to exit secsi sector mode.
66 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information command definition summary command sequence (note 1) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data asynchronous read (note 7) 1ra rd reset (note 8) 1 xxx f0 autoselect (note 9) manufacturer id 4 555 aa 2aa 55 (ba) 555 90 (ba) x00 0001 device id (note 10) 6 555 aa 2aa 55 (ba) 555 90 (ba) x01 227e (ba) x0e (note 10) (ba) x0f 2200 indicator bits 4 555 aa 2aa 55 (ba) 555 90 (ba) x03 (note 12) program 4 555 aa 2aa 55 555 a0 pa data write to buffer (note 18) 6 555 aa 2aa 55 pa 25 pa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (note 22) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase/program suspend (note 15) 1ba b0 erase/program resume (note 16) 1ba 30 set configuration register 4 555 aa 2aa 55 555 d0 x00 cr read configuration register 4 555 aa 2aa 55 555 c6 x00 cr cfi query (note 18) 1 (ba) 555 98 unlock bypass mode unlock bypass entry (note 24) 3 555 aa 2aa 55 555 20 unlock bypass program (notes 13 , 14 ) 2xx a0 pa pd unlock bypass sector erase (notes 13 , 14 ) 2xx 80 sa 30 unlock bypass erase (notes 13 , 14 ) 2 xx 80 xxx 10 unlock bypass cfi (notes 13 , 14 ) 1xx 98 unlock bypass reset 2 xx 90 xxx 00 secsi sector command definitions secsi sector secsi sector entry (note 23) 3 555 aa 2aa 55 555 88 secsi sector program 6 555 aa 2aa 55 sa 25 sa wc pa pd wbl pd secsi sector read 1 00 data secsi sector exit (note 26) 4 555 aa 2aa 55 555 90 xx 00 lock register command set definitions lock lock register command set entry (note 23) 3 555 aa 2aa 55 555 40 lock register bits program (note 25) 2xx a0 77 (note 25) data lock register bits read (note 25) 1 77 (note 25) data lock register command set exit (note 26) 2xx90xx00
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 67 advance information password password protection command set definitions password protection command set entry (note 23) 3 555 aa 2aa 55 555 60 password program* 2 xx a0 00 pwd 0 xx a0 01 pwd 1 xx a0 02 pwd 2 xx a0 03 pwd 3 password read** 4 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 password unlock*** 70025000300 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 00 29 password protection command set exit (note 26) 2xx90xx00 ppb non-volatile sector protection command set definitions non-volatile sector protection command set entry (note 23) 3 555 aa 2aa 55 (ba) 555 c0 ppb program 2 xx a0 (ba) sa 00 all ppb erase (note 20) 2xx80xx30 ppb status read 1 (ba) sa rd (0) non-volatile sector protection command set exit (note 26) 2xx90xx00 ppb lock bit global non-volatile sector protection freeze command set definitions global volatile sector protection freeze command set entry (note 23) 3 555 aa 2aa 55 555 50 ppb lock bit set 2 xx a0 xx 00 ppb lock bit status read 1 xx rd (0) global volatile sector protection freeze command set exit (note 26) 2xx90xx00 * only a7-a0 used during 2nd cycle ** amax-a0 used during 1st, 2nd, 3rd, 4th cycle *** only a7-a0 used during 3rd, 4th, 5th 6th cycle volatile sector protection command set definitions dyb volatile sector protection command set entry (note 23) 3 555 aa 2aa 55 (ba) 555 e0 dyb set 2 xx a0 (ba) sa 00 dyb clear 2 xx a0 (ba) sa 01 dyb status read 1 (ba) sa rd (0) volatile sector protection command set exit (note 26) 2xx90xx00 (continued) command sequence (note 1) cycles bus cycles (notes 1 ? 6 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data addr data addr data addr data
68 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the rising edge of the avd# pulse or active edge of clk which ever comes first. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. pd(0) = secsi sector lock bit. pd(0), or bit[0]. pd(1) = persistent protection mode lock bit. pd(1), or bit[1], must be set to ?0? for protection while pd(2), bit[2] must be left as ?1?. pd(2) = password protection mode lock bit. pd(2), or bit[2], must be set to ?0? for protection while pd(1), bit[1] must be left as ?1?. pd(3) = protection mode otp bit. pd(3) or bit[3]. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a23?a14 for the ws256n uniquely select any sector. ba = address of the bank (a23, a22, a21, and a20 for the ws256n/ a22, a21, a20, that is being switched to autoselect mode, is in bypass mode, or is being erased. cr = configuration register data bits dq15?dq0. pwd3?pwd0 = password data. pd3?pd0 present four 16 bit combinations that represent the 64-bit password pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. rd(0) = dq0 protection indicator bit. if protected, dq0 = 0, if unprotected, dq0 = 1. rd(1) = dq1 protection indicator bit. if protected, dq1 = 0, if unprotected, dq1 = 1. rd(2) = dq2 protection indicator bit. if protected, dq2 = 0, if unprotected, dq2 = 1. wbl = write buffer location. address must be within the same write buffer page as pa.] wc = word count. number of write buffer locations to load minus 1. notes: 1. see table 2 for description of bus operations. 2. all values are in hexadecimal. 3. except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at rd(0) and rd(1). 4. data bits dq15?dq8 are don?t care in command sequences, except for rd, pd, wd, pwd, and pwd3-pwd0. 5. unless otherwise noted, address bits a23?a12 for the ws256n are don?t cares. 6. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 7. no unlock or command cycles required when bank is reading array data. 8. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 9. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address. see the " autoselect command sequence " section 10. ws25n6 = 2230 11. the data is 0000h for an unlocked sector and 0001h for a locked sector 12. see the " autoselect command sequence " section 13. the unlock bypass command sequence is required prior to this command sequence. 14. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 15. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 16. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 17. command is valid when device is ready to read array data or when device is in autoselect mode. 18. the total number of cycles in the command sequence is determined by the number of words written to the write buffer. the number of cycles in the command sequence is 37 for full page programming (32 words). less than 32 word programming is not recommended. 19. the entire four bus-cycle sequ ence must be entered for which portion of the password. 20. the all ppb erase command will pre-program all ppbs before erasure to prevent over-erasure of ppbs. 21. acc must be at v hh during the entire operation of this command 22. command sequence resets device for next command after write-to-buffer operation. 23. entry commands are needed to enter a specific mode to enable instructions only available within that mode. 24. write buffer programming can be initiated after unlock bypass entry. 25. if both the persistent protection mode locking bit and the password protection mode locking bit are set a the same time, the command operation will abort and return the device to the default persistent sector protection mode during 2nd bus cycle. addresses will equal 00h on all future devices, but 77h for ws256n. 26. the exit command must be issued to reset the device into read mode. otherwise the device will hang.
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 69 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq1, dq2, dq3, dq5, dq6, and dq7. ta b l e 2 0 and the following sub - sections describe the function of these bits. dq7 and dq6 each offers a method for determining whether a program or erase operation is complete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. note that the data# polling is valid only for the last word being programmed in the write-buffer-page during write buffer programming. reading data# polling status on any word other than the last word to be programmed in the write-buffer-page will return false status information. during the embedded program algorithm, the device outputs on dq7 the com - plement of the datum programmed to dq 7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro - gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status in - formation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the bank returns to the read mode. if not all selected sectors are protected, the em - bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6?dq0 while output enable (oe#) is as - serted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-dq0 will appear on successive read cycles. ta b l e 2 0 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. figure 24 in ?ac characteristics?asynchronous? shows the data# polling timing diagram.
70 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information rdy: ready the rdy is a dedicated output, controlled by ce#, that indicates the number of clock cycles in the system should write before expecting valid data. when the de - vice is configured in the synchronous mode and rdy is at logic low, the system should wait 1 clock cycle before expecting the next word of data. using the rdy configuration command sequence, rdy can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. the rdy output is at logic low if the frequency is greater than 66 mhz during the initial access in burst mode and at the boundary crossing that occurs every 128 words beginning with address 7fh. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy - cles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading figure 5. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 71 advance information array data. if not all selected sectors are protected, the embedded erase algo - rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac - tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en - ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter - natively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approxi - mately 1 ms after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional information: figure 6 , " dq6: toggle bit i " section , figure 25 (toggle bit timing diagram), and ta b l e 1 9 . toggle bit i on dq6 requires either oe# or ce# to be deasserted and reasserted to show the change in state. note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information. figure 6. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va
72 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is ac - tively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 1 9 to compare outputs for dq2 and dq6. see the following for additional information: figure 6 , the " dq6: toggle bit i " sec - tion , and figure 25 . reading toggle bits dq6/dq2 whenever the system initially begins reading toggle bit status, it must read dq7? dq0 at least twice in a row to determine whether a toggle bit is toggling. typi - cally, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the tog - gle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc - cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de - scribed in the previous paragraph. alternatively, it may choose to perform other ta b l e 1 9 . dq6 and dq2 indications if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 73 advance information system tasks. in this case, the system must start at the beginning of the algo - rithm when it returns to determine the status of the operation. refer to figure 6 for more details. dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified inter - nal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de - termine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be as - sumed to be less than 50 s, the system need not monitor dq3. see the " sector erase command sequence " section for more details. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi - tional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each sub - sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 2 0 shows the status of dq3 relative to the other status bits. dq1: write to buffer abort dq1 indicates whether a write to buffer operation was aborted. under these con - ditions dq1 produces a ?1?. the system must issue the write to buffer abort reset command sequence to return the device to reading array data. see the " write buffer programming operation " section for more details.
74 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. data are invalid for addresses in a program suspended sector. 4. dq1 indicates the write to buffer abort status during write buffer programming operations. 5. the data-bar polling algorithm should be used for write buffer programming operations. note that dq7# during write buffer programming indicates the data-bar for dq7 data for the last loaded write- buffer address location . ta b l e 2 0 . write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 (note 4) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 to gg l e n/a program suspend mode (note 3) reading within program suspended sector invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) invalid (not allowed) reading within non-program suspended sector data data data data data data erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a to gg l e n/a non-erase suspended sector data data data data data data erase-suspend-program dq7# toggle 0 n/a n/a n/a write to buffer (note 5) busy state dq7# toggle 0 n/a n/a 0 exceeded timing limits dq7# toggle 1 n/a n/a 0 abort state dq7# toggle 0 n/a n/a 1
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 75 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?65c to +125c voltage with respect to ground: all inputs and dqs except as noted below (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to v io + 0.5 v v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +2.5 v acc (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +9.5 v output short circuit current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ma notes: 1. minimum dc voltage on input or dqs is ?0.5 v. during voltage transitions, inputs or dqs may undershoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7 . maximum dc voltage on input or dqs is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 8 . 2. minimum dc input voltage on pin acc is -0.5v. during voltage transitions, acc may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 7 . maximum dc voltage on pin acc is +9.5 v, which may overshoot to 10.5 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges wireless (w) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?25c to +85c industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65 v to +1.95 v v io supply voltages: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.35 v to +1.70 v notes: operating ranges define those limits between which the functionality of the device is guaranteed. figure 7. maximum negative overshoot waveform 9 figure 8. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 1.0 v
76 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information dc characteristics cmos compatible note: 1. maximum i cc specifications are tested with v cc = v cc max. 2. v cc = v io 3. the i cc current listed is typically less than 3 ma/mhz, with oe# at v ih . 4. i cc active while embedded erase or embedded program is in progress. 5. device enters automatic sleep mode when addresses are stable for t acc + 20ns. typical sleep mode current is equal to i cc3 . 6. total current during accelerated programming is the sum of v acc and v cc currents. 7. ce# must be set high when measuring the rdy pin. parameter description test conditions ( note: 1 & 2 ) min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current (note 7) v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih , burst length = 8 54 mhz 36 54 ma 66 mhz 40 60 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 16 54 mhz 32 48 ma 66 mhz 36 54 ma ce# = v il , oe# = v ih , we# = v ih , burst length = 32 54 mhz 28 42 ma 66 mhz 32 48 ma ce# = v il , oe# = v ih , we# = v ih , burst length = continuous 54 mhz 24 36 ma 66 mhz 28 42 ma i io1 v io non-active output oe# = v ih 20 30 a i cc1 v cc active asynchronous read current (note 3) ce# = v il , oe# = v ih , we# = v ih 10 mhz 30 36 ma 5 mhz 15 18 ma 1 mhz 3 4 ma i cc2 v cc active write current (note 4) ce# = v il , oe# = v ih , acc = v ih v acc 1 5 a v cc <35 <52.5 ma i cc3 v cc standby current (note 5) ce# = reset# = v cc 0.2 v v acc 1 5 a v cc 20 30 a i cc4 v cc reset current reset# = v il, clk = v il 20 30 a i cc5 v cc active current (read while write) ce# = v il , oe# = v ih , acc = v ih <50 <60 ma i cc6 v cc sleep current ce# = v il , oe# = v ih 20 30 a i acc accelerated program current (note 6) ce# = v il , oe# = v ih, v acc = 9.5 v v acc <30 <20 ma v cc <15 <20 ma v il input low voltage v io = 1.8 v ?0.5 0.4 v v ih input high voltage v io = 1.8 v v io ? 0.4 v io + 0.4 v ol output low voltage i ol = 100 a, v cc = v cc min = v io 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min = v io v io ? 0.1 v v hh voltage for accelerated program 8.5 9.5 v v lko low v cc lock-out voltage 1.0 1.4 v
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 77 advance information test conditions switching waveforms figure 9. te s t s e t u p ta b l e 2 1 . test specifications test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 3.0 @ 54, 66 mhz ns input pulse levels 0.0?v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v ta b l e 2 2 . key to switching waveforms waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) figure 10. input waveforms and measurement levels c l device under te s t v io 0.0 v output measurement level input v io /2 v io /2 all inputs and outputs
78 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information v cc power-up note: 1. v cc >= v io - 100mv and v cc ramp rate is > 1v / 100s 2. v cc ramp rate <1v / 100s, a hardware reset will be required. figure 11. v cc power-up diagram pin capacitance parameter description te s t s e t u p speed unit t vcs v cc setup time min 1 ms t vios v io setup time min 50 s symbol parameter te s t c o n d i t i o n ty p max unit c in1 input capacitance v in =0 4.2 5.0 pf c in2 output capacitance v out =0 5.4 8.5 pf c out control capacitance v in =0 3.9 4.7 pf v cc v io reset# t vc t vio
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 79 advance information ac characteristics?synchronous clk characterization parameter description 54 mhz 66 mhz unit f clk clk frequency max 54 66 mhz t clk clk period min 18.5 15.1 ns t ch clk high time min 7.4 6.1 ns t cl clk low time t cr clk rise time max 3 3 ns t cf clk fall time figure 12. clk characterization t clk t cl t ch t cr t cf clk t clk t cl t ch t cr t cf clk divider
80 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information synchronous/burst read @ v io = 1.8 v notes: 1. addresses are latched on the first of either the active edge of clk or the rising edge of avd#. 2. clock divider option parameter description 54 mhz 66 mhz unit jedec standard t iacc latency max 69 ns t bacc burst access time valid clock to output delay max 13.5 11.2 ns t acs address setup time to clk (note 1) min 5 4 ns t ach address hold time from clk (note 1) min 7 6 ns t bdh data hold time from next clock cycle min 4 3 ns t cr chip enable to rdy valid max 13.5 11.2 ns t oe output enable to output valid max 13.5 11.2 ns t cez chip enable to high z max 10 8 ns t oez output enable to high z max 10 8 ns t ces ce# setup time to clk min 5 4 ns t rdys rdy setup time to clk min 5 4 ns t racc ready access time from clk max 13.5 11.2 ns t aas address setup time to avd# (note 1) min 5 4 ns t aah address hold time to avd# (note 1) min 7 6 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk min 5 4 ns t avd avd# pulse min 12 10 ns t cka clk to access resume max 13.5 11.2 ns t ckz clk to high z max 10 8 ns t oes output enable setup time min 5 4 ns t rcc read cycle for continuous suspend max 1 ms
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 81 advance information timing diagrams notes: 1. figure shows total number of wait states set to five cycles. the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode. figure 13. clk synchronous burst mode read (rising active clk) da da + 1 da + n oe# data (n) addresses aa avd# rdy (n) clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 5 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z hi-z hi-z 1 2 34 56 7 t rdys t bacc da + 3 da + 2 da da + 1 da + n data (n + 1) rdy (n + 1) hi-z hi-z hi-z da + 2 da + 2 da da + 1 da + n data (n + 2) rdy (n + 2) hi-z hi-z hi-z da + 1 da + 1 da da da + n data (n + 3) rdy (n + 3) hi-z hi-z hi-z da da t cr
82 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycl es. clock is set for active rising edge. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode. figure 14. synchronous burst mode read notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycl es. clock is set for active rising edge. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in synchronous mode with wrap around. 4. dq0?dq7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 4th address in range (ac). figure 15. eight-word linear burst with wrap around da da + 1 da + n oe# data addresses aa avd# rdy clk ce# t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1234567 t rdys t bacc t acc t cr dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df db 7 cycles for initial access shown. hi-z t racc 1 234567 t rdys t bacc t cr d8 t racc
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 83 advance information notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycl es. clock is set for active rising edge. 2. if any burst address occurs at ?address + 1?, ?address + 2?, or ?address + 3?, additional clock delay cycles are inserted, and are indicated by rdy. 3. the device is in asynchronous mode with out wrap around. 4. dq?dq7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. starting address in figure is the 4th address in range (ac). figure 16. eight-word linear burst without wrap around notes: 1. figure assumes 6 wait states for initial access and synchronous read. 2. the set configuration register command sequence has b een written with cr8=0; device will output rdy one cycle before valid data. figure 17. linear burst with rdy set one cycle before data dc dd oe# data addresses ac avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t iacc t bdh de df d13 7 cycles for initial access shown. hi-z t racc 1 234567 t rdys t bacc t cr d10 t racc da+1 da da+2 da+3 da + n oe# data addresses aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t bdh 6 wait cycles for initial access shown. hi-z hi-z hi-z 1 23456 t rdys t bacc t cr
84 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information ac characteristics?asynchronous asynchronous mode read @ v io ps = 1.8 v notes: 1. asynchronous access time is from the last of eith er stable addresses or the falling edge of avd#. 2. not 100% tested. timing diagrams parameter description 54 mhz 66 mhz unit jedec standard t ce access time from ce# low max 70 70 ns t acc asynchronous access time (note 1) max 70 70 ns t avdp avd# low time min 12 10 ns t aavds address setup time to rising edge of avd# min 5 4 ns t aavdh address hold time from rising edge of avd# min 7 6 ns t oe output enable to output valid max 13.5 11.2 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 10 8 ns t oez output enable to high z (note 2) max 10 8 ns t cas ce# setup time to avd# min 0 ns note: ra = read address, rd = read data. figure 18. asynchronous mode read with latched addresses t ce we# addresses ce# oe# valid rd t acc t oeh t o data t oez t aavdh t avdp t aavds avd# ra t cas
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 85 advance information hardware reset (reset#) note: not 100% tested. note: ra = read address, rd = read data. figure 19. asynchronous mode read parameter description all speed options unit jedec std t rp reset# pulse width min 1 ms t rh reset high time before read (during embedded algorithms) to read mode (see note ) min 30 s reset high time before read (not during embedded algorithms) to read mode (see note ) figure 20. reset timings t ce we# addresses ce# oe# valid rd t acc t oeh t o data t oez avd# ra reset# t rp ce#, oe# t rh
86 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information erase/program operations @ v io = 1.8 v notes: 1. not 100% tested. 2. asynchronous read mode allows asynchronous progra m operation only. synchronous read mode allows both asynchronous and synchronous program operation. 3. in asynchronous program operation timing, addresses are latched on the falling edge of we#. in synchronous program operation timing, addresses are latched on the active edge of clk or rising edge of avd#. 4. see the ?erase and programming performance? section for more information. 5. does not include the preprogramming time. parameter description 54 mhz 66 mhz unit jedec standard t avav t wc write cycle time (note 1) min 70 70 ns t avwl t as address setup time (notes 2 , 3 ) synchronous min 5 4 ns asynchronous 0 t wlax t ah address hold time (notes 2 , 3 ) synchronous min 7 6 ns asynchronous 20 t avdp avd# low time min 12 10 ns t dvwh t ds data setup time min 45 20 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 25 ns t whwl t wph write pulse width high min 20 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 4) typ <9.4 s t whwh1 t whwh1 accelerated programming operation (note 4) typ <4 s t whwh2 t whwh2 sector erase operation (notes 4 , 5 ) typ 0.4 sec chip erase operation (notes 4 , 5 ) <104 (ws256n) t vid v acc rise and fall time min 500 ns t vids v acc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t elwl t cs ce# setup time to we# min 5 4 ns t avsw avd# setup time to we# min 5 4 ns t avhw avd# hold time to we# min 5 4 ns t avsc avd# setup time to clk min 5 4 ns t avhc avd# hold time to clk min 5 4 ns t csw clock setup time to we# min 5 ns
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 87 advance information notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a23?a14 for the ws256n are don?t care during command sequence unlock cycles. 4. clk can be either v il or v ih . 5. the asynchronous programming operation is indepe ndent of the set device read mode bit in the configuration register. figure 21. asynchronous program operation timings: we# latched addresses oe# ce# data addresses avd we# clk v cc 555h pd t as t avs t avh t a t wc t wph pa t vc t w t d t c in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avd a0h t cs t ca
88 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a23?a14 for the ws256n are don?t care during command sequence unlock cycles. 4. addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 5. either ce# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is dependent of the set device read mode bit in the configuration register. the configuration register must be set to the synchronous read mode. figure 22. synchronous program operation timings: clk latched addresses note: use setup and hold times from conventional program operation. figure 23. accelerated unlock bypass programming timing oe# ce# data addresses avd we# clk v cc 555h pd t wc t wph t wp pa t vc t d t c in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t as t ca t ah t avch t csw t avsc ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id 1 ms v il or v ih t vid t vids
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 89 advance information notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling will output true data. figure 24. data# polling timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. figure 25. toggle bit timings (during embedded algorithm) we# ce# oe# high t oe high addresses avd# t oeh t ce t ch t oez t cez status status t acc va va data we# ce# oe# high t oe high addresses avd# t oeh t ce t ch t oez t cez status status t acc va va data
90 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. rdy is active with data (dq8 = 0 in the configuration register). when dq8 = 1 in the configuration register, rdy is active one clock cycle before data. figure 26. synchronous data polling timings/toggle bit timings note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6 figure 27. dq2 vs. dq6 ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 91 advance information notes: 1. rdy active with data (dq8 = 0 in the configuration register). 2. rdy active one clock cycle before data (dq8 = 1 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device not crossing a bank in the process of performing an erase or program. 5. rdy will not go low and no additional wait states will be required if the burst frequency is <=66 mhz and the boundary crossing bit (dq14) in the configuration register is set to 0 figure 28. latency with boundary crossing when frequency > 66 mhz notes: 1. rdy active with data (dq8 = 0 in the configuration register). 2. rdy active one clock cycle before data (dq8 = 1 in the configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. 4. figure shows the device crossing a bank in the process of performing an erase or program. 5. rdy will not go low and no additional wait states will be required if the burst frequency is <=66 mhz and the boundary crossing bit (dq14) in the configuration register is set to 0 figure 29. latency with boundary crossing into program/erase bank clk address (hex) c124 c125 c126 c127 c127 c128 c129 c130 c131 d124 d125 d126 d127 d128 d129 d130 (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f 80 81 82 83 latency rdy(2) latency t racc t racc t racc t racc clk address (hex) c124 c125 c126 c127 c127 d124 d125 d126 d127 read status (stays high) avd# rdy(1) data oe#, ce# (stays low) address boundary occurs every 128 words, beginning at address 00007fh: (0000ffh, 00017fh, etc.) address 000000h is also a boundary crossing. 7c 7d 7e 7f 7f latency rdy(2) latency t racc t racc t racc t racc
92 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) s71ws512ne0bfwzz_00_ a1 june 28, 2004 advance information wait state configuration register setup: dq13, dq12, dq11 = ?111? ? reserved dq13, dq12, dq11 = ?110? ? reserved dq13, dq12, dq11 = ?101? ? 5 programmed, 7 total dq13, dq12, dq11 = ?100? ? 4 programmed, 6 total dq13, dq12, dq11 = ?011? ? 3 programmed, 5 total dq13, dq12, dq11 = ?010? ? 2 programmed, 4 total dq13, dq12, dq11 = ?001? ? 1 programmed, 3 total dq13, dq12, dq11 = ?000? ? 0 programmed, 2 total note: figure assumes address dq0 is not at an address boundary, active clock edge is rising, and wait state is set to ?101?. figure 30. example of wait states insertion note: breakpoints in waveforms indicate that system may alte rnately read array data from the ?non-busy bank? while checking the status of the program or erase operation in the ?busy? bank. the system should read status twice to ensure valid information. figure 31. back-to-back read/write cycle timings data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following addresses being latched rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45 oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t d t rc t rc t oe t as t ah t acc t oeh t w t ghwl t oez t wc t sr/ last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wp
june 28, 2004 s71ws512ne0bfwzz_00_a1 s29wsxxxn mirrorbit? flash family for multi-chip products (mcp) 93 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 1.8 v v cc , 10,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 1.65 v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. based upon single word programming, not page programming. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to exec ute the two- or four-bus-cycle sequence for the program command. see the " command definition summary " section for further information on command definitions. 6. contact the local sales office for minimum cycling endu rance values in specific applications and operating conditions. parameter ty p (note 1) max (note 2) unit comments sector erase time 64 kword vcc <0.4 2.5 s excludes 00h programming prior to erasure (note 4) 16 kword vcc <0.15 2 chip erase time vcc <104 (ws256n) <208 (ws256n) s acc <86.7(ws256n) <173.4 (ws256n) effective word programming time utilizing program write buffer vcc <9.4 <18.8 s acc <4 <8 total 32-word buffer programming time vcc <300 <600 s acc <64 <128 chip programming time (note 3) vcc <335.5 (ws256n) <671 (ws256n) s excludes system level overhead (note 5) acc <145.9 (ws256n) <292 (ws256n) erase suspend/erase resume <20 s program suspend/program resume <20 s
94 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary 128m b psram (8m word x 16 bit) pseudo sram with page & burst features ? fast access cycle time t ce =70ns max ? 8 words page read access capability t paa =20ns max ? burst read/write access capability t ac =11ns max ? low voltage operating condition v dd =+2.6 to +3.1v ? v ddq =+1.65v to +1.95v ? wide operating temperature t a =-30c to +85c ? byte control by ub# and lb# ? low power consumption i dda1 =35ma max i dds1 =300 ma max ? various power down mode sleep, 16m-bit and 32m-bit partial
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 95 preliminary function truth table asynchronous operation (page mode) note: l = v il , h = v ih , x can be either v il or v ih , high-z = high impedance *1: should not be kept this logic condition longer than 1ms. please contact local fujitsu representative for the relaxation of 1ms limitation. *2: power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of partial size. refer to "power down" in functional description for the details. *3: "l" for address pass through and "h" for address latch on the rising edge of adv#. *4: oe# can be v il during write operation if the following conditions are satisfied; (1) write pulse is initiated by ce#1 (refer to ce#1 controlled write timing), or cycle time of the previous operation cycle is satisfied. (2) oe# stays v il during write cycle. *5: can be either v il or v ih but must be valid before read or write. *6: output is either valid or high-z depending on the level of ub# and lb# input. mode note ce2ps2 ce#1ps clk adv# we# oe# lb# ub# a22-0 dq0-7 dq8-15 rdy standby (deselect) h h x x x x x x x high-z high-z high-z output disable *1 h l x *3 h h x x *5 high-z high-z high-z output disable (no read) x *3 h l h h valid high-z high-z high-z read (upper byte) x *3 h l valid high-z output valid high-z read (lower byte) x *3 l h valid output valid high-z high-z read (word) x *3 l l valid output valid output valid high-z page read x *3 l/h l/h valid *6 *6 high-z no write x *3 l *4 h h h valid invalid invalid high-z write (upper byte) x *3 h l valid invalid input valid high-z write (lower byte) x *3 l h valid input valid invalid high-z write (word) x *3 l l valid input valid input valid high-z power down *2 l x x x x x x x x high-z high-z high-z
96 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary function truth table (continued) synchronous operation (burst mode) notes:l = v il , h = v ih , x can be either v il or v ih , = valid edge, = positive edge of low pulse, high-z = high impedance *1: should not be kept this logic condition longer than 4ms. please contact local fujitsu representative for the relaxation of 4ms limitation. *2: power down mode can be entered from standby state and all dq pins are in high-z state. data retention depends on the selection of partial size. refer to "power down" in functional description for the details. *3: valid clock edge shall be set on either positive or negative edge through cr set. clk must be started and stable prior to memory access. *4: can be either v il or v ih except for the case the both of oe# and we# are v il . it is prohibited to bring the both of oe# and we# to v il *5: when device is operating in "we# single clock pulse control" mode, we# is don?t care once write operation is determined by we# low pulse at the beginnig of write access together with address latching. write suspend feature is not supported in "we# single clock pulse control" mode *6: can be either v il or v ih but must be valid before read or write is determined. and once ub# and lb# inputs are determined, they must not be changed until the end of burst. *7: once valid address is determined, input address must not be changed during adv#=l. *8: if oe#=l, output is either invalid or high-z de pending on the level of ub# and lb# input. if we#=l, input is invalid. if oe#=we#=h, output is high-z. *9: output is either valid or high-z depending on the level of ub# and lb# input. *10: input is either valid or invalid depending on the level of ub# and lb# input. *11: output is either high-z or invalid depending on the level of oe# and we# input. *12: keep the level from previous cycle except for suspen ding on last data. refere to "wait# output function" in functional description for the details. *13: wait# output is driven in high level during write operation. mode note ce2 ce#1 clk adv# we# oe# lb# ub# a22-0 dq8-1 dq16-9 wait# standby (deselect) h h x x x x x x x high-z high-z high-z start address latch *1 l *3 *4 x *4 x *6 x *6 x *7 valid *8 high-z *8 high-z *11 high-z advance burst read to next address *1 *3 h h l x *9 output valid *9 output valid output valid burst read suspend *1 *3 h high-z high-z *12 high advance burst write to next address *1 *3 *5 l h *10 input valid *10 input valid *13 high burst write suspend *1 *3 *5 h input invalid input invalid *12 high te r m i n a te burst read x h x high-z high-z high-z te r m i n a te burst write x x h high-z high-z high-z power down *2 l x x x x x x x x high-z high-z high-z
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 97 preliminary state diagram note: assuming all the parameters specified in ac characteristics are satisfied. refer to the functional descrip- tion, ac characteristics, and timing diagram for details. asynchronous operation (page mode) synchronous operation (burst mode) common state cr set power down standby standby standby output disable write read power up pause time ce2=l ce2=h ce#1=l ce#1 =h ce2=ce#1=h ce#1=l & oe#=l ce#1=l & we#=l ce#1=h ce#1=h oe#=l we#=h oe#=h we#=l address change or byte control byte control byte control @oe#=l standby write read ce2=ce#1=h ce#1=l, adv# low pulse, & oe#=l ce#1=h adv# low pulse adv# low pulse (@bl=8 or 16, and after burst operationis completed) ce#1=h read suspend oe#=h we#=l adv# low pulse initial/standby state asynchronous operation synchronous operation power down ce2=l ce2=h @m=0 @m=1 write suspend we#=h oe#=l ce#1=l, adv# low pulse, & we#=l ce#1=h ce#1=h
98 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary functional description this device supports asynchronous page read & normal write operation and syn - chronous burst read & burst write operation for faster memory access and features three kinds of power down modes for power saving as user configuable option. power-up it is required to follow the power-up timing to start executing proper device operation. refer to power-up timing. after power-up, the device defaults to asynchronous page read & normal write operation mode with sleep power down feature. configuration register the configuration register (cr) is used to configure the type of device function among optional features. each selection of features is set through cr set sequence after power-up. if cr set sequence is not performed after power-up, the device is configured for asynchronous operation with sleep power down feature as default configuration cr set sequence the cr set requires total 6 read/write operation with unique address. between each read/write operation requires that device being in standby mode. following table shows the detail sequence. the first cycle is to read from most significant address (msb). the second and third cycle are to write back the data (rda) read by first cycle. if the second or third cycle is written into the different address, the cr set is cancelled and the data written by the second or third cycle is valid as a normal write operation. the forth and fifth cycle is to write to msb. the data of forth and fifth cycle is don?t-care. if the forth or fifth cycle is written into different address, the cr set is also cancelled but write data may not be written as normal write operation. the last cycle is to read from specific address key for mode selection. and read data (rdb) is invalid. once this cr set sequence is performed from an initial cr set to the other new cr set, the written data stored in memory cell array may be lost. so, it should perform the cr set sequence prior to regular read/write operation if necessary to change from default configuration. cycle # operation address data 1st read 7fffffh (msb) read data (rda) 2nd write 7fffffh rda 3rd write 7fffffh rda 4th write 7fffffh x 5th write 7fffffh x 6th read address key read data (rdb)
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 99 preliminary functional description (continued) address key the address key has the following format. notes *1: a22, a21, a8, and a6 to a0 must be all "1" in any cases. *2: it is prohibited to apply this key. *3: if m=0, all the registers must be set with appropriate key input at the same time. *4: if m=1, ps must be set with appropriate key input at the same time. except for ps, all the other key inputs must be "1". *5: burst read & single write is not supported at we# single clock pulse control. address pin register name function key description note a22-a21 ? ? 1 unused bits muse be 1 *1 a20-a19 ps partial size 00 32m partial 01 16m partial 10 reserved for future use *2 11 sleep [default] a18-a16 bl burst length 000 reserved for future use *2 001 reserved for future use *2 010 8 words 011 16 words 100 reserved for future use *2 101 reserved for future use *2 110 reserved for future use *2 111 continuous a15 m mode 0 synchronous mode (burst read / write) *3 1 asynchronous mode[default] (page read / normal write) *4 a14-a12 rl read latency 000 reserved for future use *2 001 3 clocks 010 4 clocks 011 5 clocks 1xx reserved for future use *2 a11 bs burst sequence 0 reserved for future use *2 1 sequential a10 sw single write 0 burst read & burst write 1 burst read & single write *5 a9 ve valid clock edge 0 falling clock edge 1 rising clock edge a8 ? ? 1 unused bits muse be 1 *1 a7 wc write control 0 we# single clock pulse control without write suspend function *5 1 we# level control with write suspend function a6-a0 ? ? 1 unused bits muse be 1 *1
100 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary functional description (continued) power down the power down is low power idle state controlled by ce2. ce2 low drives the device in power down mode and mains low power idle state as long as ce2 is kept low. ce2 high resume the device from power down mode. this device has three power down modes, sleep, 16m partial, and 32m partial. the selection of power down mode is set through cr set sequence. each mode has following data retention features. the default state is sleep and it is the lowest power consumption but all data will be lost once ce2 is brought to low for power down. it is not required to perform cr set sequence to set to sleep mode after power-up in case of asynchronous operation. mode data retention size retention address sleep [default] no n/a 16m partial 16m bit 000000h to 0fffffh 32m partial 32m bit 000000h to 1fffffh
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 101 preliminary functional description (continued) burst read/write operation synchronous burst read/write operation provides faster memory access that synchronized to microcontroller or system bus frequency. configuration register set is required to perform burst read & write operation after power-up. once cr set sequence is performed to select synchronous burst mode, the device is configured to synchronous burst read/write operation mode with corresponding rl and bl that is set through cr set sequence together with operation mode. in order to perform synchronous burst read & write operation, it is required to control new signals, clk, adv# and wait# that low power srams don?t have. address adv# clk dq valid ce#1 oe# wait# high-z high-z rl bl q 2 q bl q 1 we# high address adv# clk dq valid ce#1 oe# wait# high-z high-z rl-1 bl d 2 d bl d 1 we# high burst read operation burst write operation
102 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary functional description (continued) clk input function the clk is input signal to synchronize memory to microcontroller or system bus frequency during synchronous burst read & write operation. the clk input increments device internal address counter and the valid edge of clk is referred for latency counts from address latch, burst write data latch, and burst read data out. during synchronous operation mode, clk input must be supplied except for standby state and power down state. clk is don?t care during asynchronous operation. adv# input function the adv# is input signal to indicate vali d address presence on address inputs. it is applicable to synchronous operation as well as asynchronous operation. adv# input is active during ce#1=l and ce#1=h disables adv# input. all the address are determined on the positive edge of adv#. during synchronous burst read/write operation, adv#=h disables all address inputs. once adv# is brought to high after valid address latch, it is inhibited to bring adv# low until the end of burst or until burst operation is terminated. adv# low pulse is mandatory for synchronous burst read/write operation mode to latch the valid address input. during asynchronous operation, adv#=h also disables all address inputs. adv# can be tied to low during asynchronous operation and it is not necessary to control adv# to high. wait# output function the wait# is output signal to indicate data bus status when the device is operating in synchronous burst mode. during burst read operation, wait# output is enabled after specified time duration from oe#=l. wait# output low indicates data out at next clock cycle is invalid, and wait# output becomes high one clock cycle prior to valid data out. during oe# read suspend, wait# output doesn?t indicate data bus status but carries the same level from previous clock cycle (kept high) except for read suspend on the final data output. if final read data out is suspended, wait# output become high impedance after specified time duration from oe#=h. during burst write operation, wait# output is enabled to high level after specified time duration from we#=l and kept high for entire write cycles including we# write suspend. the actual write data latching starts on the appropriate clock edge with respect to valid click edge, read latency and burst length. during we# write suspend, wait# output doesn?t indicate data bus status but carries the same level from previous clock cycle (kept high) except for write suspend on the final data input. if final write data in is suspended, wait# output become high impedance after specified time duration from we#=h. this device doesn?t incur additional delay against accrossing device-row boundary or internal refresh orepation. therefore, the burst operation is always started after fixed latency with respect to read latency. and there is no waitting cycle asserted in the middle of burst operation except for burst suspend by oe# brought to high or we# brought to high. thus, once wait# output is enabled and brought to high, wait# output keep high level until the end of burst or until the burst operation is terminated. when the device is operating in asynchronous mode, wait# output is always in high impedance.
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 103 preliminary functional description (continued) latency read latency (rl) is the number of clock cycles between the address being latched and first read data becoming available during synchronous burst read operation. it is set through cr set sequence after power-up. once specific rl is set through cr set sequence, write latency, that is the number of clock cycles between address being latched and first write data being latched, is automatically set to rl-1. the burst operation is always started after fixed latency with respect to read latency set in cr. address adv# clk valid q1 q2 q3 d1 d2 d3 d4 0 12 345 rl=3 q4 d5 dq [out] dq [in] ce#1 oe# or we# wait# wait# 6 q5 d5 q1 q2 d1 d2 d3 rl=4 q3 d4 dq [out] dq [in] wait# wait# q4 d5 q1 d1 d2 rl=5 q2 d3 dq [out] dq [in] wait# wait# q3 d4 high-z high-z high-z high-z high-z high-z
104 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary functional description (continued) address latch by adv# the adv# indicates valid address presence on address inputs. during synchronous burst read/write operation mode, all the address are determined on the positive edge of adv# when ce#1=l. the specified minimum value of adv#=l setup time and hold time against valid edge of clock where rl count begin must be satisfied for appropriate rl counts. valid address must be determined with specified setup time against either the negative edge of adv# or negative edge of ce#1 whichever comes late. and the determined valid address must not be changed during adv#=l period. burst length burst length is the number of word to be read or write during synchronous burst read/write operation as the result of a single address latch cycle. it can be set on 8, 16 words boundary or continuous for entire address through cr set sequence. the burst type is sequential that is incremental decoding scheme within a boundary address. starting from initial address being latched, device internal address counter assign +1 to the previous address until reaching the end of boundary address and then wrap round to least significant address (=0). after completing read data out or write data latch for the set burst length, operation automatically ended except for continuous burst length. when continuous burst length is set, read/write is endless unless it is terminated by the positive edge of ce#1. single write single write is synchronous write operation with burst length =1. the device can be configured either to "burst read & single write" or to "burst read & burst write" through cr set sequence. once the device is configured to "burst read & single write" mode, the burst length for syncronous write operation is always fixed 1 regardless of bl values set in cr, while burst length for read is in accordance with bl values set in cr.
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 105 preliminary write control the device has two type of we# signal control method, "we# level control" and "we# single clock pulse control", for synchronous write operation. it is configured through cr set sequence. address adv# clk valid 0 12 345 ce#1 we# 6 d1 d2 rl=5 d3 dq [in] wait# d4 we# d1 dq2 d3 dq [in] wait# d4 high-z t wld high-z t wsck t ckwh t wlth t wlth we# level control we# single clock pulse control
106 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary functional description (continued) burst read suspend burst read operation can be suspended by oe# high pulse. during burst read operation, oe# brought to high suspends burst read operation. once oe# is brought to high with the specified set up time against clock where the data being suspended, the device internal counter is suspended, and the data output become high impedance after specified time duration. it is inhibited to suspend the first data out at the beginning of burst read. oe# brought to low resumes burst read operation. once oe# is brought to low, data output become valid after specified time duration, and internal address counter is reactivated. the last data out being suspended as the result of oe#=h and first data out as the result of oe#=l are the from the same address. burst write suspend burst write operation can be suspended by we# high pulse. during burst write operation, we# brought to high suspends burst write operation. once we# is brought to high with the specified set up time against clock where the data being suspended, device internal counter is su spended, data input is ignored. it is inhibited to suspend the first data input at the beginning of burst write. we# brought to low resumes burst write operation. once we# is brought to low, data input become valid after specified time duration, and internal address counter is reactivated. the write address of the cycle where data being suspended and the first write address as the result of we#=l are the same address. burst write suspend function is available when the device is operating in we# level controlled burst write only. q 2 dq oe# clk q 1 t ac t ckqx t olz t ac q 2 t ckqx t ac q 3 t ckqx t ac t ckoh t osck t ckoh t osck t ohz wait# t cktv q 4 dq we# d 1 t dhck t dsck t d- d 2 t dhck t dsck t d- d 3 t dhck t dsck t dsck t ckwh t wsck t ckwh t wsck d 2 d 4 wait# high clk
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 107 preliminary functional description (continued) burst read termination burst read operation can be terminated by ce#1 brought to high. if bl is set on continuous, burst read operation is continued endless unless terminated by ce#1=h. it is inhibited to terminate burst read before first data out is completed. in order to guarantee last data output, the specified minimum value of ce#1=l hold time from clock edge must be satisfied. after termination, the specified minimum recovery time is required to start new access. burst write termination burst write operation can be terminated by ce#1 brought to high. if bl is set on continuous, burst write operation is continued endless unless terminated by ce#1=h. it is inhibited to terminate burst write before first data in is completed. in order to guarantee last write data being latched, the specified minimum values of ce#1=l hold time from clock edge must be satisfied. after termination, the specified minimum recovery time is required to start new access. address adv# dq oe# clk valid ce#1 wait# q 1 q 2 t ohz t ac t ckqx t ckclh t trb t ckoh t chz high-z address adv# dq we# clk valid ce#1 wait# t ckclh t trb t ckwh t chz high-z d 2 d 1 t dhck t dhck t d- t d-
108 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary absolute maximum ratings (see warning below.) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions (see warning below.) (referenced to v ss ) notes *1: maximum dc voltage on input and dq pins are v ddq +0.2v. during voltage transitions, inputs may positive overshoot to v ddq +1.0v for periods of up to 5 ns. *2: minimum dc voltage on input or dq pins are -0.3v. during voltage transitions, inputs may negative overshoot v ss to -1.0v for periods of up to 5ns. warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the device?s electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the lis ted conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit voltage of v dd supply relative to v ss v dd -0.5 to +3.6 v voltage of v ddq supply relative to v ss v ddq -0.5 to +2.6 v voltage at any pin relative to v ss v in , v out -0.5 to +2.6 v short circuit output current i out + 50 ma storage temperature t stg -55 to +125 o c parameter notes symbol min. max. unit supply voltage v dd 2.6 3.1 v dq supply voltage v ddq 1.65 1.95 v ground v ss 0 0 v high level input voltage *1 v ih v ddq *0.8 v ddq +0.2 v low level input voltage *2 v il -0.3 v ddq *0.2 v ambient temperature t a -30 85 c
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 109 preliminary dc characteristics (under recommended operating cond itions unless otherwise noted) note *1,*2,*3 notes *1: all voltages are referenced to vss. *2: dc characteristics are measured after following power-up timing. *3: i out depends on the output load conditions. parameter symbol test conditions min. max. unit input leakage current i li v in = v ss to v ddq -1.0 +1.0 a output leakage current i lo v out = v ss to v ddq , output disable -1.0 +1.0 a output high voltage level v oh v ddq = v ddq (min), i oh = ?0.5ma 1.4 ? v output low voltage level v ol i ol = 1ma ? 0.4 v v dd power down current i ddps v dd = v dd max., v ddq = v ddq max., v in = v ih or v il , ce2 0.2v sleep ? 10 a i ddp16 16m partial ? 120 a i ddp32 32m partial ? 150 a v dd standby current i dds v dd = v dd max., v ddq = v ddq max., v in (including clk)= v ih or v il , ce#1 = ce2 = v ih ? 1.5 ma i dds1 v dd = v dd max., v ddq = v ddq max., v in (including clk) 0.2v or v in (including clk) v ddq ? 0.2v, ce#1 = ce2 v ddq ? 0.2v ? 300 a i dds2 v dd = v dd max., v ddq = v ddq max., tck=min. v in 0.2v or v in v ddq ? 0.2v, ce#1 = ce2 v ddq ? 0.2v ? 350 a v dd active current i dda1 v dd = v dd max., v ddq = v ddq max., v in = v ih or v il , ce#1 = v il and ce2= v ih , i out =0ma t rc / t wc = minimum ? 35 ma i dda2 t rc / t wc = 1 s ? 5 ma v dd page read current i dda3 v dd = v dd max., v ddq = v ddq max., v in = v ih or v il , ce#1 = v il and ce2= v ih , i out =0ma, t prc = min. ? 15 ma v dd burst access current i dda4 v dd = v dd max., v ddq = v ddq max., v in = v ih or v il , ce#1 = v il and ce2= v ih , t ck = t ck min., bl = continuous, i out =0ma, ? 30 ma
110 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary ac characteristics (under recommended operating conditions unless otherwise noted) asynchronous read operation (page mode) notes *1: maximum value is applicable if ce#1 is kept at low without change of address input of a3 to a22. if needed by system operation, please contact loca l fujitsu representative for the relaxation of 1ms limitation. *2: address should not be changed within minimum t rc . *3: the output load 50pf with 50ohm termination to v ddq *0.5 v. *4: the output load 5pf without any other load. *5: applicable to a3 to a22 when ce#1 is kept at low. *6: applicable only to a0, a1 and a2 when ce#1 is kept at low for the page address access. *7: in case page read cycle is continued with keeping ce#1 stays low, ce#1 must be brought to high within 4ms. in other words, page read cycle must be closed within 4ms. *8: t vpl is specified from the negative edge of either ce#1 or adv# whichever comes late. *9: applicable when at le ast two of address inputs among applicable are switched from previous state. *10: t rc (min) and t prc (min) must be satisfied. parameter symbol value unit notes min. max. read cycle time t rc 70 1000 ns *1, *2 ce#1 access time t ce ? 70 ns *3 oe# access time t oe ? 40 ns *3 address access time t aa ? 70 ns *3, *5 adv# access time t av 70 ns *3 lb#, ub# access time t ba ? 30 ns *3 page address access time t paa ? 20 ns *3, *6 page read cycle time t prc 20 1000 ns *1, *6, *7 output data hold time t oh 5 ? ns *3 ce#1 low to output low-z t clz 5 ? ns *4 oe# low to output low-z t olz 0 ? ns *4 lb#, ub# low to output low-z t blz 0 ? ns *4 ce#1 high to output high-z t chz ? 20 ns *3 oe# high to output high-z t ohz ? 20 ns *3 lb#, ub# high to output high-z t bhz ? 20 ns *3 address setup time to ce#1 low t asc ?5 ? ns address setup time to oe# low t aso 10 ? ns adv# low pulse width t vpl 10 ? ns *8 address hold time from adv# high t ahv 5 ? ns address invalid time t ax ? 10 ns *5, *9 address hold time from ce#1 high t chah ?5 ? ns *10 address hold time from oe# high t ohah ?5 ? ns ce#1 high pulse width t cp 15 ? ns
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 111 preliminary ac characteristics (continued) asynchronous write operation notes *1: maximum value is applicable if ce#1 is kept at low without any address change. if the relaxation is needed by system operation, please contact local fujitsu representative for the relaxation of 1ms limitation. *2: minimum value must be equal or greater than the sum of write pulse (t cw , t wp or t bw ) and write recovery time (t wrc , t wr or t br ). *3: write pulse is defined from high to low transition of ce#1, we# or lb# / ub#, whichever occurs last. *4: t vpl is specified from the negative edge of either ce#1 or adv# whichever comes late. *5: write recovery is defined from low to high transition of ce#1, we# or lb# / ub#, whichever occurs first. *6: if oe# is low after minimum t ohcl , read cycle is initiated. in other word, oe# must be brought to high within 5ns after ce#1 is brought to low. once read cycle is initiated, new write pulse should be input after minimum t rc is met. *7: if oe# is low after new address input, read cycle is initiated. in other word, oe# must be brought to high at the same time or before new address valid. once read cycle is initiated, new write pulse should be input after minimum t rc is met and data bus is in high-z. parameter symbol value unit notes min. max. write cycle time t wc 70 1000 ns *1, *2 address setup time t as 0 ? ns *3 adv# low pulse width t vpl 10 ? ns *4 address hold time from adv# high t ahv 5 ? ns ce#1 write pulse width t cw 45 ? ns *3 we# write pulse width t wp 45 ? ns *3 lb#, ub# write pulse width t bw 45 ? ns *3 ce#1 write recovery time t wrc 15 ? ns *5 we# write recovery time t wr 15 1000 ns *5 lb#, ub# write recovery time t br 15 1000 ns *5 data setup time t ds 15 ? ns data hold time t dh 0 ? ns oe# high to ce#1 low setup time for write t ohcl ?5 ? ns *6 oe# high to address setup time for write t oes 0 ? ns *7 lb#, ub# write pulse overlap t bwo 30 ? ns ce#1 high pulse width t cp 15 ? ns
112 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary ac characteristics (continued) synchronous operation - clock input (burst mode) notes *1: clock period is defined between valid clock edge. *2: clock rise/fall time is defined between v ih min. and v il max. synchronous operation - address latch (burst mode) notes *1: t ascl is applicable if ce#1 brought to low after adv# is brought to low under the condition where t vlcl is satisfied. the both of t ascl and t asvl must be satisfied if t vlcl is not satisfied. *2: t vpl is specified from the negative edge of either ce#1 or adv# whichever comes late. *3: applicable to the 1st valid clock edge. parameter symbol value unit notes min. max. clock period rl=5 t ck 13 ? ns *1 rl=4 18 ? ns *1 rl=3 30 ? ns *1 clock high time t ckh 4 ? ns clock low time t ckl 4 ? ns clock rise/fall time t ckt ? 3 ns *2 parameter symbol value unit notes min. max. address setup time to adv# low t asvl ?5 ? ns *1 address setup time to ce#1 low t ascl ?5 ? ns *1 address hold time from adv# high t ahv 5 ? ns adv# low pulse width t vpl 10 ? ns *2 adv# low setup time to clk t vsck 5 ? ns *3 adv# low setup time to ce#1 low t vlcl 5 ? ns *1 ce#1 low setup time to clk t clck 5 ? ns *3 adv# low hold time from clk t ckvh 1 ? ns *3 burst end adv high hold time from clk t vhvl 13 ? ns
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 113 preliminary ac characteristics (continued) synchronous read operation (burst mode) notes *1: the output load 50pf with 50ohm termination to v ddq *0.5 v. *2: the output load 5pf without any other load. *3: once they are determined, they must not be changed until the end of burst. *4: defined from the low to high transition of ce#1 to the high to low transition of either adv# or ce#1 whichever occurs late. parameter symbol value unit notes min. max. burst read cycle time t rcb ? 8000 ns clk access time t ac ? 11 ns *1 output hold time from clk t ckqx 3 ? ns *1 ce#1 low to wait# low t cltl 5 20 ns *1 oe# low to wait# low t oltl 0 20 ns *1 adv# low to wait# low t vltl 0 20 ns *1 clk to wait# valid time t cktv ? 11 ns *1 wait# valid hold time from clk t cktx 3 ? ns *1 ce#1 low to output low-z t clz 5 ? ns *2 oe# low to output low-z t olz 0 ? ns *2 lb#, ub# low to output low-z t blz 0 ? ns *2 ce#1 high to output high-z t chz ? 20 ns *1 oe# high to output high-z t ohz ? 20 ns *1 lb#, ub# high to output high-z t bhz ? 20 ns *1 ce#1 high to wait# high-z t chtz ? 20 ns *1 oe# high to wait# high-z t ohtz ? 20 ns *1 oe# low setup time to 1st data-out t olq 30 ? ns ub#, lb# setup time to 1st data-out t bsq 26 ? ns *3 oe# setup time to clk t osck 5 ? ns oe# hold time from clk t ckoh 5 ? ns burst end ce#1 low hold time from clk t ckclh 5 ? ns burst end ub#, lb# hold time from clk t ckbh 5 ? ns burst terminate recovery time bl=8,16 t trb 26 ? ns *4 bl=continuous 70 ? ns *4
114 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary ac characteristics (continued) synchronous write operation (burst mode) notes *1: defined from the valid input edge to the high to lo w transition of either adv#, ce#1, or we#, whichever occurs last. and once they are determined, they must not be changed until the end of burst. *2: the output load 50pf with 50ohm termination to v ddq *0.5 v. *3: defined from the valid clock edge where last data-in being latched at the end of burst write to the high to low transition of either adv# or ce#1 whichever occurs late for the next access. *4: defined from the low to high transition of ce#1 to the high to low transition of either adv# or ce#1 whichever occurs late for the next access. parameter symbol value unit notes min. max. burst write cycle time t wcb ? 8000 ns data setup time to clock t dsck 5 ? ns data hold time from clk t dhck 3 ? ns we# low setup time to 1st data in t wld 30 ? ns ub#, lb# setup time for write t bs ?5 ? ns *1 we# setup time to clk t wsck 5 ? ns we# hold time from clk t ckwh 5 ? ns ce#1 low to wait# high t clth 5 20 ns *2 we# low to wait# high t wlth 0 20 ns *2 ce#1 high to wait# high-z t chtz ? 20 ns *2 we# high to wait# high-z t whtz ? 20 ns *2 burst end ce#1 low hold time from clk t ckclh 5 ? ns burst end ce#1 high setup time to next clk t chck 5 ? ns burst end ub#, lb# hold time from clk t ckbh 5 ? ns burst write recovery time t wrb 26 ns *3 burst terminate recovery time bl=8,16 t trb 26 ? ns *4 bl=continuous t trb 70 ? ns *4
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 115 preliminary ac characteristics (continued) power down parameters notes *1: applicable also to power-up. *2: applicable when partial mode is set. other timing parameters notes *1: some data might be written into any address location if t chwx (min) is not satisfied. *2: except for clock input transition time. *3: the input transition time (t t ) at ac testing is shown in below. if actual t t is longer than specified values, it may violate ac specification of some timing parameters. parameter symbol value unit note min. max. ce2 low setup time for power down entry t csp 20 ? ns *1 ce2 low hold time after power down entry t c2lp 70 ? ns *1 ce#1 high hold time following ce2 high after power down exit [sleep mode only] t chh 300 ? s *1 ce#1 high hold time following ce2 high after power down exit [not in sleep mode] t chhp 1 ? s *2 ce#1 high setup time following ce2 high after power down exit t chs 0 ? s *1 parameter symbol value unit note min. max. ce#1 high to oe# invalid time for standby entry t chox 10 ? ns ce#1 high to we# invalid time for standby entry t chwx 10 ? ns *1 ce2 high hold time after power-up t c2hl 50 ? s ce#1 high hold time following ce2 high after power-up t chh 300 ? s input transition time (except for clk) t t 1 25 s *2, *3
116 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary ac characteristics (continued) ac test conditions ac measurement output load circuit symbol description test setup value unit note v ih input high level v iops * 0.8 v v il input low level v iops * 0.2 v v ref input timing measurement level v iops * 0.5 v t t input transition time async. between v il and v ih 5 ns sync. 3 ns device under test v ccps v ddq *0.5v v ss out 0.1 f 50pf 50ohm v ccps v ss 0.1 f
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 117 preliminary timing diagrams asynchronous read timing #1-1 (basic timing) . note: this timing diagram assumes ce2=h and we#=h. asynchronous read timing #1-2 (basic timing) note: this timing diagram assumes ce2=h and we#=h. t ce valid data output address ce#1 dq (output) oe# t chz t rc t olz t chah t cp address valid t asc t asc t ohz t oh t bhz lb# / ub# t oe t ba t blz adv# low t ce valid data output address ce#1 dq (output) oe# t chz t rc t olz t cp t asc t asc t ohz t oh t bhz lb# / ub# t oe t ba t blz adv# address valid t ahv t vpl t av
118 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) asynchronous read timing #2 (oe# & address access) notes: this timing diagram assumes ce2=h, adv#=l and we#=h. asynchronous read timing #3 (lb# / ub# byte access) note: this timing diagram assumes ce2=h, adv#=l and we#=h. t aa valid data output address ce#1 dq (output) lb# / ub# t ohz t oe t rc t olz address valid valid data output address valid t rc t oh t oh oe# t ax low t aa t ohah t aso t aa valid data output address ce#1, dq0-7 (output) ub# t bhz t ba t rc t blz address valid valid data output t bhz t oh lb# t ax low t ba t ax dq8-15 (output) t blz t ba t blz t oh t bhz t oh valid data output
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 119 preliminary timing diagrams (continued) asynchronous read timing #4 (page address access after ce#1 control access) notes: this timing diagram assumes ce2=h and we#=h. asynchronous read timing #5 (random and page address access) notes *1: this timing diagram assumes ce2=h, adv#=l and we#=h. *2: either or both lb# and ub# must be low when both ce#1 and oe# are low. valid data output (normal access) address (a2-a0) ce#1 dq (output) oe# t chz t ce t rc t clz address valid valid data output (page access) address valid t prc t oh t oh t chah t paa address (a22-a3) address valid lb# / ub# t paa t oh t prc t paa t prc t oh address valid address valid t rc adv# t asc valid data output (normal access) address (a2-a0) ce#1 dq (output) oe# t oe t rc t olz t blz t aa valid data output (page access) address valid t prc t oh t oh t rc t paa address (a22-a3) address valid lb# / ub# t aa t oh address valid t rc t paa t prc t oh address valid address valid t rc t ax t ax t ba address valid low t aso
120 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) asynchronous write timing #1-1 (basic timing) notes: this timing diagram assumes ce2=h and adv#=l. asynchronous write timing #1-2 (basic timing) notes: this timing diagram assumes ce2=h. t as valid data input address ce#1 dq (input) we# t dh t ds t wc t wrc t wp t cw lb#, ub# t as t bw address valid t as t as t br oe# t ohcl t as t as t wr adv# low t as valid data input address ce#1 dq (input) we# t dh t ds t wc t wrc t wp t cw lb#, ub# t as t bw address valid t as t as t br oe# t ohcl t as t as t wr adv# t vpl t ahv
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 121 preliminary timing diagrams (continued) asynchronous write timing #2 (we# control) note: this timing diagram assumes ce2=h and adv#=l. asynchronous write timing #3-1 (we# / lb# / ub# byte write control) note: this timing diagram assumes ce2=h, adv#=l and oe#=h. t as address we# ce#1 t wc t wr t wp lb#, ub# address valid t as t wr t wp valid data input dq (input) t dh t ds oe# t oes t ohz t wc valid data input t dh t ds low address valid t ohah t as address we# ce#1 t wc t br t wp lb# address valid t as t br t wp valid data input dq0-7 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq8-15 (input)
122 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) asynchronous write timing #3-2 (we# / lb# / ub# byte write control) note: this timing diagram assumes ce2=h, adv#=l and oe#=h. asynchronous write timing #3-3 (we# / lb# / ub# byte write control) note: this timing diagram assumes ce2=h, adv#=l and oe#=h. t as address we# ce#1 t wc t wr t bw lb# address valid t as t wr t bw valid data input dq0-7 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq8-15 (input) t as address we# ce#1 t wc t br t bw lb# address valid t as t br t bw valid data input dq0-7 (input) t dh t ds ub# t wc valid data input t dh t ds low address valid dq8-15 (input)
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 123 preliminary timing diagrams (continued) asynchronous write timing #3-4 (we# / lb# / ub# byte write control) note: this timing diagram assumes ce2=h, adv#=l and oe#=h. t as address we# ce#1 t wc t br t bw lb# address valid t as t br t bw dq1-8 (input) t dh t ds ub# t wc t dh t ds low address valid dq9-16 (input) t dh t ds t as t br t bw t as t br t bw t dh t ds valid data input valid data input valid data input valid data input t bwo t bwo
124 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) asynchronous read / write timing #1-1 (ce#1 control) notes *1: this timing diagram assumes ce2=h and adv#=l. *2: write address is valid from either ce#1 or we# of last falling edge. asynchronous read / write timing #1-2 (ce#1 / we# / oe# control) notes *1: this timing diagram assumes ce2=h and adv#=l. *2: oe# can be fixed low during write operation if it is ce#1 controlled write at read-write-read sequence. read data output address ce#1 dq we# t wc t cw oe# t ohcl ub#, lb# t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wrc t chah t dh t clz t oh read data output address ce#1 dq we# t wc t wp oe# t ohcl ub#, lb# t oe t chah t cp write address t as t rc write data input t ds t chz t oh t cp t ce t asc read address t wr t chah t dh t olz t oh read data output
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 125 preliminary timing diagrams (continued) asynchronous read / write timing #2 (oe#, we# control) notes *1: this timing diagram assumes ce2=h and adv#=l. *2: ce#1 can be tied to low for we# and oe# controlled operation. asynchronous read / write timing #3 (oe#, we#, lb#, ub# control) notes *1: this timing diagram assumes ce2=h and adv#=l. *2: ce#1 can be tied to low for we# and oe# controlled operation. read data output address ce#1 dq we# t wc t wp oe# ub#, lb# t oe write address t as t rc write data input t ds t ohz t oh t aa read address t wr t dh t olz t oh read data output t ohz low t aso t ohah t oes t ohah read data output address ce#1 dq we# t wc t bw oe# ub#, lb# t ba write address t as t rc write data input t ds t bhz t oh t aa read address t br t dh t blz t oh read data output t bhz low t aso t ohah t ohah t oe
126 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) clock input timing notes *1: stable clock input must be required during ce#1=l. *2: t ck is defined between valid clock edge. *3: t ckt is defined between v ih min. and v il max. address latch timing (synchronous mode) notes *1: case #1 is the timing when ce#1 is brought to low after adv# is brought to low. case #2 is the timing when adv# is brought to low after ce#1 is brought to low. *2: t vpl is specified from the negative edge of either ce#1 or adv# whichever comes late. at least one valid clock edge must be input during adv#=l. *3: t vsck and t clck are applied to the 1st valid clock edge during adv#=l. clk t ck t ckh t ckl t ckt t ckt t ck clk adv# address ce#1 t ahv t vpl t asvl valid case #1 case #2 t vsck t ahv t vpl t vlcl valid t vsck t clck t ascl low t ckvh t ckvh
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 127 preliminary timing diagrams (continued) synchronous read timing #1 (oe# control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. t ahv address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t vpl t clck t ascl wait# q 1 t olq t ac t ckqx t oltl t ac t cktv high q bl high-z rl=5 t vsck t ohtz t olz t ac t ckqx t ohz t rcb t ckoh valid t vsck t clck t cp t vpl t vhvl high-z t blq t ckbh t ascl t asvl t cktx t ckvh t ckvh
128 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) synchronous read timing #2 (ce#1 control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl t clck t ascl wait# q 1 t ac t ckqx t ac t cktv rl=5 t vsc t ac t rcb valid t vsck t clck t cp t vpl t vhvl t cltl high t clz t ckclh t ascl t ahv q bl t chtz t clz t ckqx t chz t cltl t ckbh t asvl t cktx t ckvh t ckvh
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 129 preliminary timing diagrams (continued) synchronous read timing #3 (adv# control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl rdy q 1 t ac t ckqx t ac t cktv rl=5 t vsck t ac t rcb valid t asvl t vsck t vpl t vhvl high t ahv q bl t ckqx low low t cktx t vltl t vltl t ckvh t ckvh
130 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) synchronous write timing #1 (we# level control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl t clck t ascl rdy high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckwh t wld valid t ahv t vpl t clck t ascl t vsc t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t ckvh t ckvh t asvl
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 131 preliminary timing diagrams (continued) synchronous write timing #2 (we# single clock pulse control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 d 2 t dhck d bl t dsck t dhck t dsck t dsck t wcb t ckclh valid t asvl t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t chtz t wlth t wsck t ckwh t ckwh t wsck t ckvh t ckvh
132 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) synchronous write timing #3 (adv# control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl wait# high rl=5 t bs d 1 d 2 t dhck d bl t d- t dhck t d- t d- t wcb valid t asvl t ahv t vpl t vsck t bs t wrb t vsck t vhvl t ckbh t ckvh t ckvh high
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 133 preliminary timing diagrams (continued) synchronous write timing #4 (we# level control, single write) notes *1: this timing diagram assumes ce2=h, the valid clock edge on rising edge and single write operation. *2: write data is latched on the valid clock edge. address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl t clck t ascl wait# high high-z rl=5 t bs d 1 t dhck t dsck t wcb t ckwh t wld valid t asvl t ahv t vpl t clck t ascl t vsck t bs t cp t wrb t vsck t vhvl t ckbh t wlth t whtz t wlth t ckvh t ckvh
134 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) synchronous read to write timing #1(ce#1 control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl t clck t ascl wait# t vsck t bs t cp rl=5 d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t chtz t ac t ckqx t chz t ckqx t ckclh t ckclh t vhvl t ckbh t ckbh t wcb t clth t ckvh
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 135 preliminary timing diagrams (continued) synchronous read to write timing #2(adv# control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl wait# t bs rl=5 t ckwh d 1 d 2 t dhck t dhck t dsck t dsck d bl t dhck t dsck d 3 t dsck t dhck q bl-1 q bl t ohtz t ac t ckqx t ohz t ckqx t wld t ckoh t vhvl t ckbh t ckbh t wlth t ckvh t vsck
136 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) synchronous write to read timing #1 (ce#1 control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. d bl address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl t clck t ascl wait# t vsck t cp rl=5 t ckclh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t cltl t clz t wrb t ckbh t cktx t chtz high-z t ckvh
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 137 preliminary timing diagrams (continued) synchronous write to read timing #2 (adv# control) note: this timing diagram assumes ce2=h, the valid clock edge on rising edge and bl=8 or 16. d bl address adv# dq we# oe# lb#, ub# clk valid ce#1 t asvl t ahv t vpl wait# low t vsck rl=5 t ckwh d bl-1 t dhck t dhck t dsck t dsck q 1 q 2 t ac t ckqx t ac t ckqx t cktv t oltl t olz t olq t wrb t blq t ckbh t cktx t whtz high-z t ckvh
138 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) power-up timing #1 notes *1: v ddq shall be applied and reach the specified minimum level prior to v dd applied. *2: the both of ce#1 and ce2 shall be brought to high together with v ddq prior to v dd applied. otherwise power-up timing#2 must be applied for proper operation. *3: the t chh specifies after v dd reaches specified minimum level and applicable to both ce#1 and ce2. power-up timing #2 notes *1: v ddq shall be applied and reach specified minimum level prior to v dd applied. *2: the t c2hl specifies from ce2 low to high transition after v dd reaches specified minimum level. if ce2 became high prior to v dd reached specified minimum level, t c2hl is defined from v dd minimum. *3: ce#1 shall be brought to high prior to or together with ce2 low to high transition. ce#1 v iops 0v ce2 t chh *3 v ccps 0v *2 v ccps min *1,*2 v iops min *1 *2 ce#1 v iops v iops min *1 0v ce2 t chh v ccps 0v v ccps min *1 t c2hl *2 t chs t csp t c2lp t c2hl *2 *3
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 139 preliminary timing diagrams (continued) power down entry and exit timing note: this power down mode can be also used as a reset timing if power-up timing above could not be satisfied and power-down program was not performed prior to this reset. standby entry timing after read or write note: both t chox and t chwx define the earliest entry timing for standby mode. if either of timing is not satisfied, it takes t rc (min) period for standby mode from ce#1 low to high transition. t csp ce#1 power down entry ce2 t c2lp t chh (t chhp ) power down mode power down exit t chs dq high-z t cho ce#1 oe# we# active (read) standby active (write) standby t chwx
140 128mb psram s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary timing diagrams (continued) configuration register set timing #1 (asynchronous operation) notes *1: the all address inputs must be high from cycle #1 to #5. *2: the address key must confirm the format specified in functional description. if not, the operation and data are not guaranteed. *3: after t cp or t rc following cycle #6, the configuration register set is completed and returned to the normal operation. t cp and t rc are applicable to returning to asynchronous mode and to synchronous mode re- spectively. address ce#1 dq* 3 we# t rc oe# lb#, ub# rda msb* 1 msb* 1 msb* 1 msb* 1 msb* 1 key* 2 t wc t wc t wc t wc t rc t cp t cp t cp t cp t cp cycle #1 cycle #2 cycle #3 cycle #4 cycle #5 cycle #6 rda rda x x rdb t cp * 3 (t rc )
june 28, 2004 s71ws512ne0bfwzz_00_a1 128mb psram 141 preliminary timing diagrams (continued) configuration register set timing #2 (synchronous operation) notes *1: the all address inputs must be high from cycle #1 to #5. *2: the address key must confirm the format specified in functional description. if not, the operation and data are not guaranteed. *3: after t trb following cycle #6, the configuration register set is completed and returned to the normal operation. address adv# dq we# oe# lb#, ub# clk ce#1 rda msb rda msb rda msb x msb x msb rdb key t rcb t wcb t wcb t wcb t wcb t rcb t trb t trb t trb t trb t trb cycle#1 cycle#2 cycle#3 cycle#4 cycle#5 cycle#6 t trb rl rl-1 rl-1 rl-1 rl-1 rl
142 revision summary s71ws512ne0bfwzz_00_a1 june 28, 2004 preliminary revision summary revision a (april 27, 2004) initial release. revision a+1 (june 28, 2004) modify colophon & company name. trademarks and notice the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e ( i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages ari sing in connection with above-men- tioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au- thorization by the respective government entity will be required for export of those products. the contents of this document are subject to change without notice.this document may contain information on a spansion tm product under development by spansion llc. spansion llc reserves the right to change or discontinue work on any product without notice. the information in t his document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assumes no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004 spansion llc. all rights reserved. spansion tm , the spansion tm logo, mirrorbit, combinations thereof, and expressflash are trademarks of spansion llc. other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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